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    Method of forming a multi-level interconnect structure in a semiconductor device
    1.
    发明授权
    Method of forming a multi-level interconnect structure in a semiconductor device 有权

    公开(公告)号：US11088070B2

    公开(公告)日：2021-08-10

    申请号：US16936271

    申请日：2020-07-22

    Applicant: IMEC vzw

    Inventor： Basoene Briggs ,  Vladimir Machkaoutsan ,  Zsolt Tokei

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

    Method of patterning target layer
    2.
    发明授权
    Method of patterning target layer 审中-公开

    公开(公告)号：US10672655B2

    公开(公告)日：2020-06-02

    申请号：US15975611

    申请日：2018-05-09

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Basoene Briggs ,  Ivan Zyulkov ,  Katia Devriendt

    IPC: H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/288 ,  H01L21/285

    Abstract: The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines. In one aspect, a method for patterning a target layer comprises: forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines, filling the gaps with a sacrificial material, forming a hole by removing the sacrificial material along a portion of one of the gaps, the hole extending across the gap and exposing a surface portion of the target layer and sidewall surface portions of material lines on opposite sides of the one gap, performing a selective deposition process adapted to grow a fill material selectively on the one or more surface portions inside the hole, thereby forming a block mask extending across the gap, removing, selectively to the material lines and the block mask, the sacrificial material from the target layer to expose the gaps, the one gap being interrupted in the longitudinal direction by the block mask, and transferring a pattern including the material lines and the block mask into the target layer.

    METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210028106A1

    公开(公告)日：2021-01-28

    申请号：US16936271

    申请日：2020-07-22

    Applicant: IMEC vzw

    Inventor： Basoene Briggs ,  Vladimir Machkaoutsan ,  Zsolt Tokei

    IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

    Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

    Method for forming a multi-level interconnect structure
    4.
    发明授权
    Method for forming a multi-level interconnect structure 有权

    公开(公告)号：US10763159B2

    公开(公告)日：2020-09-01

    申请号：US16518361

    申请日：2019-07-22

    Applicant: IMEC VZW

    Inventor： Basoene Briggs ,  Christopher Wilson ,  Juergen Boemmels

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

    Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.

    METHOD FOR FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE
    6.
    发明申请
    METHOD FOR FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE 审中-公开

    公开(公告)号：US20200027780A1

    公开(公告)日：2020-01-23

    申请号：US16518361

    申请日：2019-07-22

    Applicant: IMEC VZW

    Inventor： Basoene Briggs ,  Christopher Wilson ,  Juergen Boemmels

    IPC: H01L21/768 ,  H01L23/522

    Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.

    Method for forming transistor structures
    10.
    发明授权
    Method for forming transistor structures 有权

    公开(公告)号：US11682591B2

    公开(公告)日：2023-06-20

    申请号：US17409964

    申请日：2021-08-24

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Juergen Boemmels ,  Basoene Briggs

    IPC: H01L21/84 ,  H01L27/12 ,  H01L29/775 ,  H01L21/762 ,  H01L21/8238

    CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/775 ,  H01L21/823878

    Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:



    forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and
    processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks;
    the method further comprising, prior to said processing:
    by etching removing the sacrificial layer of each layer stack to form a respective cavity on either sides of the insulating wall underneath the channel layer of the first and second layer stack, the channel layers being supported by the insulating wall; and
    depositing a bottom insulating material in said cavities;

    wherein, subsequent to said processing, the bottom insulating material forms a bottom insulating layer underneath the source region, the drain region and the channel regions on either side of the insulating wall.

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