公开(公告)号：US20170148868A1

公开(公告)日：2017-05-25

申请号：US15425596

申请日：2017-02-06

Applicant: INTEL CORPORATION

Inventor： NICK LINDERT ,  JOSEPH M. STEIGERWALD ,  KANWAL JIT SINGH

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H05K1/182 ,  H01L2924/00

Abstract: Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

公开(公告)号：US20160343665A1

公开(公告)日：2016-11-24

申请号：US15225392

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： CHRISTOPHER J. JEZEWSKI ,  DAVID J. MICHALAK ,  KANWAL JIT SINGH ,  ALAN M. MYERS

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

Abstract translation: 公开了用于在多孔电介质材料中形成互连的技术。 根据一些实施例，可以通过用诸如氮化钛（TiN），二氧化钛（TiO 2）或其它合适的牺牲材料的牺牲孔填充材料填充其孔来临时减小主介质层的孔隙率， 与互连的金属化和介电材料相比，具有高蚀刻选择性。 在填充电介质层内形成互连之后，可以从主电介质的孔中去除牺牲孔填充材料。 在某些情况下，可以对主介电层的介电常数（κ值），泄漏性能和/或时间依赖的介电击穿（TDDB）性能产生最小或其他可忽略的影响来进行去除和固化。 一些实施例可以用于例如涉及基于原子层沉积（ALD）的和/或化学气相沉积（CVD）的高多孔，超低κ（ULK）电介质材料的后端金属化的工艺。