公开(公告)号：US20180095692A1

公开(公告)日：2018-04-05

申请号：US15283074

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Mahesh S. NATU ,  Vedaraman GEETHA

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0685 ,  G06F12/0802 ,  G06F12/0868 ,  G06F12/1416 ,  G06F12/1458 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/214

Abstract: In one embodiment, a memory interface employs selective memory mode authorization enforcement in accordance with the present description to ensure that memory modes of operation which have not been authorized, are not permitted to proceed. In one embodiment, mode control logic receives from memory control logic of the memory interface, memory mode selection data which is compared to a mode authorization classification structure to determine if the memory mode being selected in association with a memory transaction request is authorized or otherwise permitted. Memory mode enablement logic of the mode control logic enables the requested memory mode associated with a memory transaction request if it is determined that the selected memory mode associated with the memory transaction request is authorized. Other aspects are described herein.

公开(公告)号：US20240272911A1

公开(公告)日：2024-08-15

申请号：US18645295

申请日：2024-04-24

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Eswaramoorthi NALLUSAMY ,  Anand K. ENAMANDRAM ,  Mahesh S. NATU ,  Eric J. DEHAEMER ,  Filip SCHMOLE ,  Bharat S. PILLILLI

IPC: G06F9/4401

CPC classification number: G06F9/4403

Abstract: Examples described herein relate to an apparatus that includes an interface and circuitry to: prior to boot of a processor, configure a memory address decoder to increase a memory region size associated with firmware access from a first size to a second size, wherein the second size is larger than the first size. In some examples, the memory address decoder is to decode an address space in a Serial Peripheral Interface (SPI) flash device to determine a location of a Firmware Interface Table (FIT) in the second size of the memory region and the second circuitry is to access an entry in the FIT to determine a location of a boot firmware.

公开(公告)号：US20190034264A1

公开(公告)日：2019-01-31

申请号：US15846170

申请日：2017-12-18

Applicant: INTEL CORPORATION

Inventor： Sivakumar RADHAKRISHNAN ,  Malay TRIVEDI ,  Jayasekhar THOLIYIL ,  Erik A. MCSHANE ,  Roger W. LIU ,  Mahesh S. NATU

IPC: G06F11/07

Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

公开(公告)号：US20250085977A1

公开(公告)日：2025-03-13

申请号：US18955177

申请日：2024-11-21

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Mahesh S. NATU ,  Eswaramoorthi NALLUSAMY ,  Tiffany J. KASANICKY

IPC: G06F9/4401 ,  G06F9/50

Abstract: Examples described herein relate to allocating different lanes of an interface to different processor socket partitions and causing a processor socket partition to boot by accessing firmware by routing a request for the firmware to a device via one or more lanes of the interface and receiving the firmware from the one or more lanes. In some examples, the first host interface circuitry is to route an access to system address space for the first boot firmware to a particular lane of the first host interface circuitry.

公开(公告)号：US20240264759A1

公开(公告)日：2024-08-08

申请号：US18622005

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Anand K. ENAMANDRAM ,  Kerry VANDER KAMP ,  Mahesh S. NATU ,  Robert A. BRANCH

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0683

Abstract: A Cloud Service Provider reconfigures a memory subsystem during routine operation, while minimizing the amount of time a server is not online. Server downtime is reduced by offloading reconfiguration of system memory to the operating system with platform assistance. The operating system enumerates potential memory configurations of the memory subsystem with associated performance characteristics in an abstracted manner and performs reconfiguration of the memory subsystem without a cold reset. When reconfiguration of the memory subsystem is deemed necessary by the operating system, the operating system examines the enumerated memory subsystem configurations provided by system firmware. After selecting the memory subsystem configuration, the operating system initiates a reconfiguration process. The reconfiguration process saves any existing memory context to an auxiliary device, requests system firmware to perform the memory subsystem reconfiguration, and restores the existing memory context from the auxiliary device after the memory subsystem reconfiguration has been completed.