公开(公告)号：US20220197852A1

公开(公告)日：2022-06-23

申请号：US17692031

申请日：2022-03-10

Applicant: Intel Corporation

Inventor： Mohan Nair ,  Ishwar Agarwal ,  Ashish Gupta ,  Peeyush Purohit ,  Vijay Pothi Raj Govindaraj ,  Nitish Paliwal ,  Rahul Boyapati ,  Minjer Juan

IPC: G06F15/173 ,  G06F9/50

Abstract: A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

公开(公告)号：US10762244B2

公开(公告)日：2020-09-01

申请号：US16024022

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Joshua Fender ,  Utkarsh Y. Kakaiya ,  Mohan Nair ,  Brian Morris ,  Pratik Marolia

IPC: G06F21/00 ,  G06F21/76 ,  H04L29/08 ,  G06F11/14 ,  G06F1/3206 ,  G06F21/54 ,  G06F1/324 ,  G06F21/74 ,  H04L29/06 ,  G06F1/20 ,  G06F1/3287

Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

公开(公告)号：US09122811B2

公开(公告)日：2015-09-01

申请号：US13968504

申请日：2013-08-16

Applicant: INTEL CORPORATION

Inventor： Michael Klinglesmith ,  Mohan Nair ,  Joseph Murray

IPC: H04L12/66 ,  G06F13/00 ,  G06F13/40 ,  H04L12/64 ,  H04L12/18 ,  H04L12/40 ,  G06F13/42 ,  G06F13/10 ,  H04L29/08

CPC classification number: G06F13/4027 ,  G06F13/105 ,  G06F13/4221 ,  G06F2213/0026 ,  H04L12/1845 ,  H04L12/40032 ,  H04L12/6418 ,  H04L29/08468 ,  H04L67/1078

Abstract: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明涉及一种具有耦合在上游结构和集成设备结构之间的虚拟端口的集成端点，该虚拟端口包括多功能逻辑，以处理与一个或多个知识产权（IP） 集成设备结构。 集成设备结构具有在IP块和上行结构之间传送数据和命令信息的主要信道和用于在IP块和多功能逻辑之间传送边带信息的边带信道。 描述和要求保护其他实施例。

公开(公告)号：US11372787B2

公开(公告)日：2022-06-28

申请号：US15836854

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Utkarsh Kakaiya ,  Nagabhushan Chitlur ,  Rajesh M. Sankaran ,  Mohan Nair ,  Pratik M. Marolia

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42 ,  G06F12/10 ,  G06F12/1036

Abstract: There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.

公开(公告)号：US20190034367A1

公开(公告)日：2019-01-31

申请号：US15836854

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Utkarsh Kakaiya ,  Nagabhushan Chitlur ,  Rajesh M. Sankaran ,  Mohan Nair ,  Pratik M. Marolia

IPC: G06F13/20 ,  G06F13/40

Abstract: There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.