公开(公告)号：US20250112122A1

公开(公告)日：2025-04-03

申请号：US18477906

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Kevin P. O'Brien ,  Paul Gutwin ,  David L. Kencke ,  Mahmut Sami Kavrik ,  Daniel Chanemougame ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Uygar E. Avci ,  Tristan A. Tronic ,  Chelsey Dorow ,  Andrey Vyatskikh ,  Rachel A. Steinhardt ,  Chia-Ching Lin ,  Chi-Yin Cheng ,  Yu-Jin Chen ,  Tyrone Wilson

IPC: H01L23/48 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/18 ,  H01L29/423 ,  H01L29/78

Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.

公开(公告)号：US20240222461A1

公开(公告)日：2024-07-04

申请号：US18091201

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Ande Kitamura ,  Carl H. Naylor ,  Kevin O'Brien ,  Kirby Maxey ,  Chelsey Dorow ,  Ashish Verma Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz ,  Chia-Ching Lin ,  Sudarat Lee ,  Mahmut Sami Kavrik ,  Carly Rogan ,  Paul Gutwin

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/443 ,  H01L23/528 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/775

CPC classification number: H01L29/45 ,  H01L21/02568 ,  H01L21/443 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/775

Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.