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公开(公告)号:US09825095B2
公开(公告)日:2017-11-21
申请号:US15247710
申请日:2016-08-25
Applicant: INTEL CORPORATION
Inventor: Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
CPC classification number: H01L27/2436 , H01L29/66477 , H01L29/66568 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L2029/7858
Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
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公开(公告)号:US20170323928A1
公开(公告)日:2017-11-09
申请号:US15658078
申请日:2017-07-24
Applicant: INTEL CORPORATION
Inventor: Brian S. Doyle , David L. Kencke , Charles C. Kuo , Dmitri E. Nikonov , Robert S. Chau
CPC classification number: H01L27/228 , G11C11/161 , G11C11/1659 , H01L43/02 , H01L43/08
Abstract: The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
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3.
公开(公告)号:US10707409B2
公开(公告)日:2020-07-07
申请号:US15882546
申请日:2018-01-29
Applicant: INTEL CORPORATION
Inventor: Charles C. Kuo , Kaan Oguz , Brian S. Doyle , Mark L. Doczy , David L. Kencke , Satyarth Suri , Robert S. Chau
Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.
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公开(公告)号:US20180301619A1
公开(公告)日:2018-10-18
申请号:US15735616
申请日:2015-06-26
Applicant: Intel Corporation
Inventor: Kaan Oguz , Kevin P. O'Brien , Brian S. Doyle , David L. Kencke , Charles C. Kuo , Robert S. Chau
Abstract: An embodiment includes an apparatus comprising: a substrate; and a perpendicular magnetic tunnel junction (pMTJ) comprising a fixed layer and first and second free layers; wherein (a) the first free layer includes Cobalt (Co), Iron (Fe), and Boron (B), and (b) the second free layer is epitaxial and includes Manganese (Mn) and Gallium (Ga). Other embodiments are described herein.
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5.
公开(公告)号:US20180166625A1
公开(公告)日:2018-06-14
申请号:US15882546
申请日:2018-01-29
Applicant: INTEL CORPORATION
Inventor: Charles C. Kuo , Kaan Oguz , Brian S. Doyle , Mark L. Doczy , David L. Kencke , Satyarth Suri , Robert S. Chau
CPC classification number: H01L43/08 , G11C11/161 , H01L43/02 , H01L43/12
Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.
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6.
公开(公告)号:US09496486B2
公开(公告)日:2016-11-15
申请号:US14812655
申请日:2015-07-29
Applicant: Intel Corporation
Inventor: Brian S. Doyle , David L. Kencke , Charles C. Kuo , Uday Shah , Kaan Oguz , Mark L. Doczy , Satyarth Suri , Clair Webb
CPC classification number: H01L43/12 , G11C11/161 , G11C11/1659 , H01L27/222 , H01L27/228 , H01L29/66007 , H01L29/82 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
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公开(公告)号:US09455343B2
公开(公告)日:2016-09-27
申请号:US14040574
申请日:2013-09-27
Applicant: INTEL CORPORATION
Inventor: Ravi Pillarisetty , Brian S. Doyle , Elijah V. Karpov , David L. Kencke , Uday Shah , Charles C. Kuo , Robert S. Chau
CPC classification number: H01L27/2436 , H01L29/66477 , H01L29/66568 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L2029/7858
Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
Abstract translation: 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。
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公开(公告)号:US09231194B2
公开(公告)日:2016-01-05
申请号:US13996603
申请日:2013-03-28
Applicant: Intel Corporation
Inventor: Charles C. Kuo , Kaan Oguz , Brian S. Doyle , Elijah V. Karpov , Roksana Golizadeh Mojarad , David L. Kencke , Robert S. Chau
CPC classification number: H01L43/10 , G11C11/161 , H01F10/3286 , H01F10/329 , H01L43/065 , H01L43/08 , H01L43/12 , H01L43/14
Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less stable memory having a MTJ with only a single oxide layer. Other embodiments are described herein.
Abstract translation: 实施例包括在自由层和固定层之间包括自由磁性层,固定磁性层和隧道势垒的磁性隧道结(MTJ); 所述隧道势垒直接接触所述自由层的第一侧; 和直接接触自由层的第二面的氧化物层; 其中所述隧道势垒包括氧化物并且具有第一电阻区域(RA)产物,并且所述氧化物层具有低于所述第一RA产物的第二RA产物。 MTJ可以包括在垂直旋转扭矩传递存储器中。 隧道势垒和氧化物层形成具有高稳定性的存储器,RA产物没有实质上高于具有仅具有单一氧化物层的MTJ的较不稳定的存储器。 本文描述了其它实施例。
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公开(公告)号:US20200051724A1
公开(公告)日:2020-02-13
申请号:US15735622
申请日:2015-06-26
Applicant: Intel Corporation
Inventor: Brian S. Doyle , Kaan Oguz , Kevin P. O'Brien , David L. Kencke , Charles C. Kuo , Mark L. Doczy , Satyarth Suri , Robert S. Chau
IPC: H01F10/193 , H01F10/32 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.
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公开(公告)号:US10522739B2
公开(公告)日:2019-12-31
申请号:US15735616
申请日:2015-06-26
Applicant: Intel Corporation
Inventor: Kaan Oguz , Kevin P. O'Brien , Brian S. Doyle , David L. Kencke , Charles C. Kuo , Robert S. Chau
Abstract: An embodiment includes an apparatus comprising: a substrate; and a perpendicular magnetic tunnel junction (pMTJ) comprising a fixed layer and first and second free layers; wherein (a) the first free layer includes Cobalt (Co), Iron (Fe), and Boron (B), and (b) the second free layer is epitaxial and includes Manganese (Mn) and Gallium (Ga). Other embodiments are described herein.
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