公开(公告)号：US20210265482A1

公开(公告)日：2021-08-26

申请号：US17239439

申请日：2021-04-23

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20170309734A1

公开(公告)日：2017-10-26

申请号：US15626067

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Suman DATTA ,  Mantu K. HUDAIT ,  Mark L. DOCZY ,  Jack T. KAVALIEROS ,  Amlan MAJUMDAR ,  Justin K. BRASK ,  Been-Yih JIN ,  Matthew V. METZ ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/205 ,  H01L27/092 ,  H01L29/15 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

公开(公告)号：US20170323972A1

公开(公告)日：2017-11-09

申请号：US15660574

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Robert S. CHAU ,  Suman DATTA ,  Jack KAVALIEROS ,  Justin K. BRASK ,  Mark L. DOCZY ,  Matthew METZ

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/267 ,  H01L29/207 ,  H01L29/45 ,  H01L29/51 ,  H01L29/16

CPC classification number: H01L29/201 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20210242325A1

公开(公告)日：2021-08-05

申请号：US17236338

申请日：2021-04-21

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20200295153A1

公开(公告)日：2020-09-17

申请号：US16889680

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.