公开(公告)号：US20170271576A1

公开(公告)日：2017-09-21

申请号：US15503680

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3295 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20210242325A1

公开(公告)日：2021-08-05

申请号：US17236338

申请日：2021-04-21

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20200295153A1

公开(公告)日：2020-09-17

申请号：US16889680

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20190006417A1

公开(公告)日：2019-01-03

申请号：US16069122

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Mark L. DOCZY ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE

IPC: H01L27/22 ,  G11C11/16

Abstract: Approaches and structures for unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bi-polar coercivity are described. In an example, a memory array includes a plurality of bitlines and a plurality of select lines. The memory array also includes a plurality of memory elements located among and coupled to the plurality of bitlines and the plurality of select lines. Each of the plurality of memory elements includes a unipolar switching magnetic tunnel junction (MTJ) device and a select device.

公开(公告)号：US20180165065A1

公开(公告)日：2018-06-14

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Justin S. BROCKMAN ,  Juan G. ALZATE VINASCO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Satyarth SURI ,  Robert S. CHAU ,  Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV

IPC: G06F7/58 ,  H01L43/08 ,  H01L43/02

CPC classification number: G06F7/588 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US20170309734A1

公开(公告)日：2017-10-26

申请号：US15626067

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Suman DATTA ,  Mantu K. HUDAIT ,  Mark L. DOCZY ,  Jack T. KAVALIEROS ,  Amlan MAJUMDAR ,  Justin K. BRASK ,  Been-Yih JIN ,  Matthew V. METZ ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/205 ,  H01L27/092 ,  H01L29/15 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

公开(公告)号：US20170200884A1

公开(公告)日：2017-07-13

申请号：US15324589

申请日：2014-08-05

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Charles C. KUO ,  Anurag CHAUDHRY ,  Robert S. CHAU

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe configurations and techniques to increase interfacial anisotropy of magnetic tunnel junctions. In embodiments, a magnetic tunnel junction may include a cap layer, a tunnel barrier, and a magnetic layer disposed between the cap layer and the tunnel barrier. A buffer layer may, in some embodiments, be disposed between the magnetic layer and a selected one of the cap layer or the tunnel barrier. In such embodiments, the interfacial anisotropy of the buffer layer and the selected one of the cap layer or the tunnel barrier may be greater than an interfacial anisotropy of the magnetic layer and the selected one of the cap layer or the tunnel barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US20210265482A1

公开(公告)日：2021-08-26

申请号：US17239439

申请日：2021-04-23

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20190378972A1

公开(公告)日：2019-12-12

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.

公开(公告)号：US20190334079A1

公开(公告)日：2019-10-31

申请号：US16463821

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Justin S. BROCKMAN ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.