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    Cryptographic computing with legacy peripheral devices
    1.
    发明授权
    Cryptographic computing with legacy peripheral devices 有权

    公开(公告)号：US12210660B2

    公开(公告)日：2025-01-28

    申请号：US17548170

    申请日：2021-12-10

    Applicant: Intel Corporation

    Inventor： Anna Trikalinou ,  Abhishek Basak ,  Rupin H. Vakharwala ,  Utkarsh Y. Kakaiya

    IPC: G06F21/83 ,  G06F21/62 ,  G06F21/78

    Abstract: In one embodiment, a read request is received from a peripheral device across an interconnect, with the read request including a process identifier and an encrypted virtual address. One or more keys are obtained based on the process identifier of the read request, and the encrypted virtual address of the read request is decrypted based on the one or more keys to obtain an unencrypted virtual address. Encrypted data is retrieved from memory based on the unencrypted virtual address, and the encrypted data is decrypted based on the one or more keys to obtain plaintext data. The plaintext data is transmitted to the peripheral device across the interconnect.

    High-performance input-output devices supporting scalable virtualization
    3.
    发明授权
    High-performance input-output devices supporting scalable virtualization 有权

    公开(公告)号：US12164971B2

    公开(公告)日：2024-12-10

    申请号：US18301733

    申请日：2023-04-17

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

    IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L61/59 ,  H04L67/2885

    Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

    System, apparatus and method for fine-grain address space selection in a processor
    10.
    发明授权
    System, apparatus and method for fine-grain address space selection in a processor 有权

    公开(公告)号：US11461099B2

    公开(公告)日：2022-10-04

    申请号：US16911441

    申请日：2020-06-25

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Gilbert Neiger ,  Philip Lantz ,  Sanjay K. Kumar

    IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

    Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

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