公开(公告)号：US20180173545A1

公开(公告)日：2018-06-21

申请号：US15843822

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

IPC: G06F9/455 ,  G06F9/445

CPC classification number: G06F9/455 ,  G06F9/44521 ,  G06F9/4552

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

公开(公告)号：US20220405210A1

公开(公告)日：2022-12-22

申请号：US17892879

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

公开(公告)号：US10761867B2

公开(公告)日：2020-09-01

申请号：US15843822

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

IPC: G06G7/48 ,  G06F9/455 ,  G06F9/445

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

公开(公告)号：US09928067B2

公开(公告)日：2018-03-27

申请号：US13976359

申请日：2012-09-21

Applicant: Intel Corporation

Inventor： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Jane Chen ,  Gang Wang ,  Yi Qian ,  Huifeng Gu

IPC: G06F9/30 ,  G06F9/45 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/30181 ,  G06F8/52 ,  G06F9/30072 ,  G06F9/3861 ,  G06F9/4552

Abstract: Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.

公开(公告)号：US09910721B2

公开(公告)日：2018-03-06

申请号：US14777065

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Yong Wu ,  Xiao Dong Lin ,  Yihua Jin ,  Xueliang Zhong ,  Jianhui Li

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/54 ,  G06F9/45 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F9/541 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/4552 ,  G06F9/45533

Abstract: Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

公开(公告)号：US09753787B2

公开(公告)日：2017-09-05

申请号：US14724394

申请日：2015-05-28

Applicant: Intel Corporation

Inventor： Yihua Jin ,  Xiao Dong Lin ,  Yong Wu ,  Jianhui Li ,  Xueliang Zhong

IPC: G06F9/54 ,  G06F12/0842 ,  G06F9/46 ,  G06F12/02

CPC classification number: G06F9/54 ,  G06F9/461 ,  G06F9/466 ,  G06F12/0284 ,  G06F12/0842 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/62

Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

公开(公告)号：US20160321178A1

公开(公告)日：2016-11-03

申请号：US14780428

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： Yong Wu ,  Xiao Dong Lin ,  Jiajia Yu ,  Xueliang Zhong

IPC: G06F12/0815 ,  G06F12/0868 ,  G06F12/0808

CPC classification number: G06F12/0815 ,  G06F9/4552 ,  G06F12/0808 ,  G06F12/0868

Abstract: Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.

Abstract translation: 系统和方法可以提供动态代码生成系统中的翻译缓存关闭和一致的数据恢复。 一种装置可以将翻译缓存组合在一起，并将整个翻译缓存快照恢复。 在保存和恢复期间，可能会维持翻译之间的链接。

公开(公告)号：US12079138B2

公开(公告)日：2024-09-03

申请号：US17892879

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/355 ,  G06F9/455

CPC classification number: G06F12/10 ,  G06F9/30174 ,  G06F9/355 ,  G06F9/45554 ,  G06F9/45558 ,  G06F2009/45583

Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

公开(公告)号：US11422943B2

公开(公告)日：2022-08-23

申请号：US15553853

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

公开(公告)号：US09767024B2

公开(公告)日：2017-09-19

申请号：US14780428

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Yong Wu ,  Xiao Dong Lin ,  Jiajia Yu ,  Xueliang Zhong

IPC: G06F9/45 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F9/455 ,  G06F12/0868

CPC classification number: G06F12/0815 ,  G06F9/4552 ,  G06F12/0808 ,  G06F12/0868

Abstract: Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.