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    High temperature ALD process for metal oxide for DRAM applications
    1.
    发明授权
    High temperature ALD process for metal oxide for DRAM applications 有权
    用于DRAM应用的金属氧化物的高温ALD工艺

    公开(公告)号：US08829647B2

    公开(公告)日：2014-09-09

    申请号：US13737156

    申请日：2013-01-09

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Edward Haywood ,  Sandra Malhotra ,  Hiroyuki Ode

    IPC: H01L29/92 ,  C23C16/455 ,  H01L21/285 ,  H01L49/02

    CPC classification number: H01L29/92 ,  C23C16/45525 ,  H01L21/28562 ,  H01L28/65 ,  H01L28/75

    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.

    Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层含有使用高温低压ALD工艺形成的导电金属氧化物。 高温ALD工艺产生了具有增强的结晶度，较高密度，降低的收缩率和较低的碳污染的层。 高温ALD工艺可以用于底部电极和顶部电极层中的一个或两个。

    Methods for Reproducible Flash Layer Deposition
    2.
    发明申请
    Methods for Reproducible Flash Layer Deposition 有权
    可再生闪蒸层沉积的方法

    公开(公告)号：US20140187018A1

    公开(公告)日：2014-07-03

    申请号：US13731452

    申请日：2012-12-31

    Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

    Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L49/02

    CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

    Abstract translation: 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

    High Work Function, Manufacturable Top Electrode
    4.
    发明申请
    High Work Function, Manufacturable Top Electrode 有权
    高功能，可制造顶电极

    公开(公告)号：US20140183697A1

    公开(公告)日：2014-07-03

    申请号：US13737263

    申请日：2013-01-09

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

    Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

    Manufacturable high-k DRAM MIM capacitor structure
    5.
    发明授权
    Manufacturable high-k DRAM MIM capacitor structure 有权

    公开(公告)号：US08679939B2

    公开(公告)日：2014-03-25

    申请号：US13737467

    申请日：2013-01-09

    Applicant: Intermolecular Inc.

    Inventor： Sandra Malhotra ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L21/20

    CPC classification number: H01L28/56 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

    Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.

    Asymmetric MIM capacitor for DRAM devices
    6.
    发明授权
    Asymmetric MIM capacitor for DRAM devices 有权
    用于DRAM器件的不对称MIM电容器

    公开(公告)号：US08575671B2

    公开(公告)日：2013-11-05

    申请号：US13692460

    申请日：2012-12-03

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

    Inventor： Hanhong Chen ,  Hiroyuki Ode

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L28/65 ,  H01L27/10805 ,  H01L28/75

    Abstract: A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.

    Abstract translation: 形成用于MIM DRAM电容器的双层第二电极，其中与电介质层（即底层）接触的电极层具有在随后的退火步骤期间耐氧化的组成并具有金红石模板能力。 实例包括SnO 2和RuO 2。 包括底层的电容器堆叠经受PMA处理以减少电介质层中的氧空位并降低电介质/第二电极界面处的界面态。 双层的另一组分（即顶层）是高功函数，高导电性金属或导电金属化合物。

    Blocking layers for leakage current reduction in DRAM devices
    7.
    发明授权
    Blocking layers for leakage current reduction in DRAM devices 有权
    阻塞层用于DRAM器件的漏电流降低

    公开(公告)号：US08574999B2

    公开(公告)日：2013-11-05

    申请号：US13738865

    申请日：2013-01-10

    Applicant: Intermolecular Inc. ,  Elpida Memory, Inc

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L21/20 ,  H01L29/94

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

    DOPED ELECTRODES FOR DRAM APPLICATIONS
    8.
    发明申请
    DOPED ELECTRODES FOR DRAM APPLICATIONS 有权
    用于DRAM应用的DOPED电极

    公开(公告)号：US20130270673A1

    公开(公告)日：2013-10-17

    申请号：US13915050

    申请日：2013-06-11

    Applicant: Elpida Memory, Inc ,  Intermolecular, Inc.

    Inventor： Xiangxin Rui ,  Hiroyuki Ode

    IPC: H01L49/02

    CPC classification number: H01L28/65 ,  H01L28/40 ,  H01L28/60

    Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode layers are conductive molybdenum oxide.

    Abstract translation: 形成用于MIM DRAM电容器的金属氧化物第一电极层，其中第一和/或第二电极层含有一个或多个掺杂剂，直到总掺杂浓度，其将不会阻止电极层在随后的退火步骤期间结晶。 一种或多种掺杂剂具有大于约5.0eV的功函数。 一种或多种掺杂剂具有小于约1000μmOcm的电阻率。 有利地，电极层是导电性氧化钼。

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