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公开(公告)号：US20150087130A1
公开(公告)日：2015-03-26
申请号：US14033326
申请日：2013-09-20
IPC分类号： H01L49/02
CPC分类号： H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
摘要翻译： 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。
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公开(公告)号：US20130217202A1
公开(公告)日：2013-08-22
申请号：US13830282
申请日：2013-03-14
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L49/02
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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公开(公告)号：US20140187018A1
公开(公告)日：2014-07-03
申请号：US13731452
申请日：2012-12-31
发明人： Sandra G. Malhotra , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L49/02
摘要： A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.
摘要翻译： 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。
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公开(公告)号：US20140187016A1
公开(公告)日：2014-07-03
申请号：US13727962
申请日：2012-12-27
IPC分类号： H01L49/02
CPC分类号： H01L29/92 , H01L28/65 , H01L28/75 , H01L51/0021 , H01L51/5206
摘要： Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.
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公开(公告)号：US08574999B2
公开(公告)日：2013-11-05
申请号：US13738865
申请日：2013-01-10
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/40
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
摘要翻译： 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。
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公开(公告)号：US09281357B2
公开(公告)日：2016-03-08
申请号：US14599843
申请日：2015-01-19
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
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公开(公告)号：US09224878B2
公开(公告)日：2015-12-29
申请号：US13727962
申请日：2012-12-27
CPC分类号： H01L29/92 , H01L28/65 , H01L28/75 , H01L51/0021 , H01L51/5206
摘要： Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.
摘要翻译： 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。
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公开(公告)号：US20150137315A1
公开(公告)日：2015-05-21
申请号：US14599843
申请日：2015-01-19
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
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公开(公告)号：US20130122683A1
公开(公告)日：2013-05-16
申请号：US13738865
申请日：2013-01-10
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/40
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
摘要翻译： 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。
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公开(公告)号：US20130119512A1
公开(公告)日：2013-05-16
申请号：US13665524
申请日：2012-10-31
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/02356 , H01L27/10852 , H01L28/75
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
摘要翻译： 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 金属氧化物第二电极层形成在电介质层的上方。 金属氧化物第二电极层具有与电介质层的晶体结构相容的晶体结构。 可选地，在金属氧化物第二电极层上形成第二电极体层。
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