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    High work function, manufacturable top electrode
    2.
    发明授权
    High work function, manufacturable top electrode 有权
    高功能，可制造顶电极

    公开(公告)号：US08847397B2

    公开(公告)日：2014-09-30

    申请号：US13737263

    申请日：2013-01-09

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

    IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L29/92 ,  H01L49/02 ,  H01L51/52

    CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

    Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

    Band gap improvement in DRAM capacitors
    4.
    发明授权
    Band gap improvement in DRAM capacitors 有权
    DRAM电容器带隙改善

    公开(公告)号：US08878269B2

    公开(公告)日：2014-11-04

    申请号：US13738831

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra G. Malhotra ,  Hiroyuki Ode

    IPC: H01L27/108

    CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

    Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

    High performance dielectric stack for DRAM capacitor
    5.
    发明授权
    High performance dielectric stack for DRAM capacitor 有权
    用于DRAM电容器的高性能电介质堆叠

    公开(公告)号：US08546236B2

    公开(公告)日：2013-10-01

    申请号：US13738866

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/20 ,  H01L21/31

    CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

    Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

    Enhanced non-noble electrode layers for DRAM capacitor cell
    6.
    发明授权
    Enhanced non-noble electrode layers for DRAM capacitor cell 有权
    用于DRAM电容器电池的增强型非贵金属电极层

    公开(公告)号：US08581318B1

    公开(公告)日：2013-11-12

    申请号：US13737209

    申请日：2013-01-09

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Wim Deweerd ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Hiroyuki Ode

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L28/60 ,  H01L28/75

    Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩcm. Advantageously, the electrode materials are conductive molybdenum oxide.

    Abstract translation: 形成用于MIM DRAM电容器的金属氧化物第一电极材料，其中第一和/或第二电极材料或结构包含具有一个或多个掺杂剂的层，直到总掺杂浓度，其将不会阻止电极材料在随后的退火期间结晶 步。 有利地，掺杂有一种或多种掺杂剂的电极具有大于约5.0eV的功函数。 有利地，掺杂有一种或多种掺杂剂的电极具有小于约1000微米的电阻率。 有利地，电极材料是导电性氧化钼。

    Method for Fabricating a DRAM Capacitor
    7.
    发明申请
    Method for Fabricating a DRAM Capacitor 有权
    制造DRAM电容器的方法

    公开(公告)号：US20130154057A1

    公开(公告)日：2013-06-20

    申请号：US13738794

    申请日：2013-01-10

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

    Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

    Abstract translation: 公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。 第一电极由导电二元金属化合物形成，并且导电二元金属化合物在还原气氛中退火以促进所需晶体结构的形成。 二元金属化合物可以是金属氧化物。 在还原气氛中退火金属氧化物（即氧化钼）可导致形成具有金红石相晶体结构的第一电极材料（即MoO 2）。 当使用TiO 2作为电介质层时，这有助于金红石相晶体结构的形成。 TiO 2的金红石相具有比其他可能的TiO 2晶体结构更高的k值，从而改善了DRAM电容器的性能。

    Band Gap Improvement In DRAM Capacitors
    8.
    发明申请
    Band Gap Improvement In DRAM Capacitors 审中-公开
    DRAM电容器带隙改进

    公开(公告)号：US20130127015A1

    公开(公告)日：2013-05-23

    申请号：US13738831

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra Malhotra ,  Hiroyuki Ode

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

    Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 化合物高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

    High Work Function, Manufacturable Top Electrode
    10.
    发明申请
    High Work Function, Manufacturable Top Electrode 有权
    高功能，可制造顶电极

    公开(公告)号：US20140183697A1

    公开(公告)日：2014-07-03

    申请号：US13737263

    申请日：2013-01-09

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

    Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

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