公开(公告)号：US10891411B2

公开(公告)日：2021-01-12

申请号：US16205197

申请日：2018-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gi-Joon Nam ,  David John Geiger ,  Paul G. Villarrubia ,  Shyam Ramji ,  Myung-Chul Kim ,  Benjamin Neil Trombley

IPC: G06F30/327 ,  G06F30/392 ,  G06F111/20

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

公开(公告)号：US12282725B2

公开(公告)日：2025-04-22

申请号：US17804070

申请日：2022-05-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alexey Y Lvov ,  Gi-Joon Nam ,  Benjamin Neil Trombley ,  Lakshmi N Reddy ,  Paul G Villarrubia

IPC: G06F30/392 ,  G06F30/27

Abstract: Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

公开(公告)号：US20240104282A1

公开(公告)日：2024-03-28

申请号：US17934216

申请日：2022-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin Neil Trombley ,  Chung-Lung K. Shum ,  Paul G. Villarrubia ,  K. Paul Muller ,  Michael Hemsley Wood ,  Daniel Arthur Gay ,  Hua Xiang ,  Karl Evan Smock Anderson ,  Erica Stuecheli ,  Michael Alexander Bowen ,  Randall J. Darden

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.

公开(公告)号：US12277375B2

公开(公告)日：2025-04-15

申请号：US17649180

申请日：2022-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hua Xiang ,  Benjamin Neil Trombley ,  Gi-Joon Nam ,  Gustavo E. Tellez ,  Paul G. Villarrubia

IPC: G06F30/392

Abstract: Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

公开(公告)号：US12188979B2

公开(公告)日：2025-01-07

申请号：US18326717

申请日：2023-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin Neil Trombley ,  Chung-Lung K. Shum ,  Karl Evan Smock Anderson ,  Bodo Hoppe ,  Erica Stuecheli ,  Shiri Moran ,  Patrick James Meaney ,  Arvind Haran ,  Douglas Balazich

IPC: G01R31/317 ,  G01R31/3181 ,  G01R31/3185

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

公开(公告)号：US20230090855A1

公开(公告)日：2023-03-23

申请号：US17479246

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Basanth Jagannathan ,  Michael Hemsley Wood ,  Leon Sigal ,  James Leland ,  Alexander Joel Suess ,  Benjamin Neil Trombley ,  Paul G. Villarrubia

IPC: H02J3/00

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

公开(公告)号：US11288425B1

公开(公告)日：2022-03-29

申请号：US17124429

申请日：2020-12-16

Applicant: International Business Machines Corporation

Inventor： Benjamin Neil Trombley ,  Nathaniel Douglas Hieter ,  Daniel Arthur Gay

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/3312 ,  G06F119/12

Abstract: Carry out an initial wire-length-driven placement for an integrated circuit design embodied in an unplaced netlist, using a computerized placer, to obtain a data structure representing initial placements of logic gates. Identify at least one timing-critical source-sink path between at least one pair of source-sink endpoints in the data structure representing the initial placements. Create a new pseudo two-pin net for each pair of the at least one pair of source-sink endpoints to create an updated netlist. Carry out a revised wire-length-driven placement on the updated netlist to obtain a data structure representing revised placements.

公开(公告)号：US20200034507A1

公开(公告)日：2020-01-30

申请号：US16048093

申请日：2018-07-27

Applicant: International Business Machines Corporation

Inventor： Alexey Y. Lvov ,  Gi-Joon Nam ,  Benjamin Neil Trombley ,  Myung-Chul Kim ,  Paul G. Villarrubia

IPC: G06F17/50 ,  G06F17/15

Abstract: A putative circuit design is represented as a set of movable blocks of predetermined size which must fit into a bounding box, with a plurality of subsets to be interconnected by wires. A total weighted wire length is determined as a function of coordinates of centers of the movable blocks by summing a half perimeter wire length over the plurality of subsets, and a density penalty is determined as a convolution of an indicator function of the current placement and a convolution kernel, via incremental integer computation without use of floating point arithmetic. Blocks are moved to minimize a penalty function which is the sum of the total weighted wire length and the product of a density penalty weight and the density penalty. The process repeats until a maximum value of the density penalty weight is reached or the density penalty approaches zero.

公开(公告)号：US11916384B2

公开(公告)日：2024-02-27

申请号：US17479246

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Basanth Jagannathan ,  Michael Hemsley Wood ,  Leon Sigal ,  James Leland ,  Alexander Joel Suess ,  Benjamin Neil Trombley ,  Paul G. Villarrubia

IPC: G05B99/00 ,  H02J3/00

CPC classification number: H02J3/0073 ,  H02J3/003 ,  H02J3/004

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

公开(公告)号：US20200175122A1

公开(公告)日：2020-06-04

申请号：US16205197

申请日：2018-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gi-Joon Nam ,  David John Geiger ,  Paul G. Villarrubia ,  Shyam Ramji ,  Myung-Chul Kim ,  Benjamin Neil Trombley

IPC: G06F17/50

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.