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    Methods for manufacturing a semiconductor device
    1.
    发明授权
    Methods for manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09368573B2

    公开(公告)日：2016-06-14

    申请号：US14139888

    申请日：2013-12-24

    Applicant: Infineon Technologies AG

    Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

    Abstract: In various embodiments, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include forming a first source/drain region, forming a second source/drain region, forming an active region electrically coupled between the first source/drain region and the second source/drain region, forming a trench disposed between the second source/drain region and at least a portion of the active region, forming a first isolation layer disposed over the bottom and the sidewalls of the trench, forming electrically conductive material disposed over the isolation layer in the trench, forming a second isolation layer disposed over the active region, and forming a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.

    Abstract translation: 在各种实施例中，提供了一种用于制造半导体器件的方法。 制造半导体器件的方法可以包括形成第一源极/漏极区域，形成第二源极/漏极区域，形成电耦合在第一源极/漏极区域与第二源极/漏极区域之间的有源区域，形成沟槽 在所述第二源极/漏极区域和所述有源区域的至少一部分之间形成设置在所述沟槽的底部和所述侧壁上的第一隔离层，形成设置在所述沟槽中的所述隔离层上方的导电材料，形成第二隔离层 层，设置在有源区上方，并且形成设置在第二隔离层上的栅极区。 导电材料可以耦合到电接触。

    METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20140113423A1

    公开(公告)日：2014-04-24

    申请号：US14139888

    申请日：2013-12-24

    Applicant: Infineon Technologies AG

    Inventor： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

    IPC: H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

    Abstract: In various embodiments, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include forming a first source/drain region, forming a second source/drain region, forming an active region electrically coupled between the first source/drain region and the second source/drain region, forming a trench disposed between the second source/drain region and at least a portion of the active region, forming a first isolation layer disposed over the bottom and the sidewalls of the trench, forming electrically conductive material disposed over the isolation layer in the trench, forming a second isolation layer disposed over the active region, and forming a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.

    Abstract translation: 在各种实施例中，提供了一种用于制造半导体器件的方法。 制造半导体器件的方法可以包括形成第一源极/漏极区域，形成第二源极/漏极区域，形成电耦合在第一源极/漏极区域与第二源极/漏极区域之间的有源区域，形成沟槽 在所述第二源极/漏极区域和所述有源区域的至少一部分之间形成设置在所述沟槽的底部和所述侧壁上的第一隔离层，形成设置在所述沟槽中的所述隔离层上方的导电材料，形成第二隔离层 层，设置在有源区上方，并且形成设置在第二隔离层上的栅极区。 导电材料可以耦合到电接触。

    High voltage semiconductor devices
    3.
    发明授权
    High voltage semiconductor devices 有权
    高压半导体器件

    公开(公告)号：US09455275B2

    公开(公告)日：2016-09-27

    申请号：US14168978

    申请日：2014-01-30

    Applicant: Infineon Technologies AG

    Inventor： Mayank Shrivastava ,  Maryam Shojaei Baghini ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

    IPC: H01L27/12 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10

    CPC classification number: H01L27/1211 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/78624

    Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

    Abstract translation: 在一个实施例中，半导体器件包括设置在衬底中的第一掺杂类型的第一源。 第一掺杂型的第一漏极设置在衬底中。 第一栅极区域设置在第一源极和第一漏极之间。 第一掺杂类型的第一沟道区域设置在第一栅极区域的下方。 第二掺杂类型与第一掺杂类型相反。 第一掺杂类型的第一延伸区域设置在第一栅极和第一漏极之间。 第一延伸区域是设置在基板中或上方的第一鳍片的一部分。 第一隔离区域设置在第一延伸区域和第一漏极之间。 第一掺杂类型的第一阱区设置在第一隔离区下。 第一阱区域将第一延伸区域与第一漏极电耦合。

    High Voltage Semiconductor Devices
    5.
    发明申请
    High Voltage Semiconductor Devices 有权
    高压半导体器件

    公开(公告)号：US20140145265A1

    公开(公告)日：2014-05-29

    申请号：US14168978

    申请日：2014-01-30

    Applicant: Infineon Technologies AG

    Inventor： Mayank Shrivastava ,  Maryam Shojaei Baghini ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

    IPC: H01L27/12

    CPC classification number: H01L27/1211 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/78624

    Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

    Abstract translation: 在一个实施例中，半导体器件包括设置在衬底中的第一掺杂类型的第一源。 第一掺杂型的第一漏极设置在衬底中。 第一栅极区域设置在第一源极和第一漏极之间。 第一掺杂类型的第一沟道区域设置在第一栅极区域的下方。 第二掺杂类型与第一掺杂类型相反。 第一掺杂类型的第一延伸区域设置在第一栅极和第一漏极之间。 第一延伸区域是设置在基板中或上方的第一鳍片的一部分。 第一隔离区域设置在第一延伸区域和第一漏极之间。 第一掺杂类型的第一阱区设置在第一隔离区下。 第一阱区域将第一延伸区域与第一漏极电耦合。

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