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1.发明申请公开(公告)号：US20190138893A1
公开(公告)日：2019-05-09
申请号：US16147176
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Abhishek SHARMA , Jack T. KAVALIEROS , Ian A. YOUNG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Uygar AVCI , Gregory K. CHEN , Amrita MATHURIYA , Raghavan KUMAR , Phil KNAG , Huseyin Ekin SUMBUL , Nazila HARATIPOUR , Van H. LE
IPC: G06N3/063 , H01L27/108 , H01L27/11 , H01L27/11502 , G06N3/04 , G06F17/16
Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.
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公开(公告)号：US20190042199A1
公开(公告)日：2019-02-07
申请号：US16147004
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Huseyin Ekin SUMBUL , Phil KNAG , Gregory K. CHEN , Raghavan KUMAR , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram KRISHNAMURTHY , Ian A. YOUNG
Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.
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公开(公告)号：US20190065151A1
公开(公告)日：2019-02-28
申请号：US16145569
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Gregory K. CHEN , Raghavan KUMAR , Huseyin Ekin SUMBUL , Phil KNAG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Abhishek SHARMA , Ian A. YOUNG
Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit x n-bit multiplications.
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4.发明申请公开(公告)号：US20190042949A1
公开(公告)日：2019-02-07
申请号：US16147143
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Ian A. YOUNG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory K. CHEN , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin Ekin SUMBUL
Abstract: A semiconductor chip is described. The semiconductor chip includes a compute-in-memory (CIM) circuit to implement a neural network in hardware. The semiconductor chip also includes at least one output that presents samples of voltages generated at a node of the CIM circuit in response to a range of neural network input values applied to the CIM circuit to optimize the CIM circuit for the neural network.
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公开(公告)号：US20200233923A1
公开(公告)日：2020-07-23
申请号：US16839013
申请日：2020-04-02
Applicant: Intel Corporation
Inventor： Phil KNAG , Gregory K. CHEN , Raghavan KUMAR , Huseyin Ekin SUMBUL , Abhishek SHARMA , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Ram KRISHNAMURTHY , Ian A. YOUNG
IPC: G06F17/16 , G06N3/063 , G11C8/08 , G11C7/12 , G11C7/10 , G06F9/30 , G11C11/56 , G11C11/418 , G11C11/419
Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.
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Patent Agency Ranking
公开(公告)号：US20200098826A1
公开(公告)日：2020-03-26
申请号：US16141025
申请日：2018-09-25
Applicant: Intel Corporation
Inventor： Abhishek SHARMA , Gregory CHEN , Phil KNAG , Ram KRISHNAMURTHY , Raghavan KUMAR , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Huseyin SUMBUL , Ian A. YOUNG
Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.
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7.发明申请公开(公告)号：US20190042928A1
公开(公告)日：2019-02-07
申请号：US16147109
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Ian A. YOUNG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory K. CHEN , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin Ekin SUMBUL
IPC: G06N3/063 , H03M7/30 , G11C5/06 , G11C11/419
Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.
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公开(公告)号：US20220012581A1
公开(公告)日：2022-01-13
申请号：US17484828
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Abhishek SHARMA , Jack T. KAVALIEROS , Ian A. YOUNG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Uygar AVCI , Gregory K. CHEN , Amrita MATHURIYA , Raghavan KUMAR , Phil KNAG , Huseyin Ekin SUMBUL , Nazila HARATIPOUR , Van H. LE
IPC: G06N3/063 , H01L27/108 , H01L27/11502 , G06N3/04 , G06F17/16 , H01L27/11 , G11C11/54 , G11C7/10
Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.
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公开(公告)号：US20190102170A1
公开(公告)日：2019-04-04
申请号：US16146430
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Gregory K. CHEN , Raghavan KUMAR , Huseyin Ekin SUMBUL , Phil KNAG , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Abhishek SHARMA , Ian A. YOUNG
IPC: G06F9/30 , G06F9/38 , G11C11/419 , G11C13/00
Abstract: A compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.
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公开(公告)号：US20190042160A1
公开(公告)日：2019-02-07
申请号：US16147024
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Raghavan KUMAR , Phil KNAG , Gregory K. CHEN , Huseyin Ekin SUMBUL , Sasikanth MANIPATRUNI , Amrita MATHURIYA , Abhishek SHARMA , Ram KRISHNAMURTHY , Ian A. YOUNG
IPC: G06F3/06 , G04F10/00 , G11C11/419 , G11C13/00 , G11C11/418
Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.
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