公开(公告)号：US20240105520A1

公开(公告)日：2024-03-28

申请号：US18534219

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Anthony ST. AMOUR ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/823475 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/7854 ,  H10B10/12

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

公开(公告)号：US20190164841A1

公开(公告)日：2019-05-30

申请号：US15859411

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Anthony ST. AMOUR ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

公开(公告)号：US20220367283A1

公开(公告)日：2022-11-17

申请号：US17867369

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Anthony ST. AMOUR ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

公开(公告)号：US20200286792A1

公开(公告)日：2020-09-10

申请号：US16881514

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Anthony ST. AMOUR ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.