公开(公告)号：US09984654B2

公开(公告)日：2018-05-29

申请号：US15595853

申请日：2017-05-15

Applicant: Intel Corporation

Inventor： Aruna Kumar ,  Prakash K. Radhakrishnan ,  Pravas Pradhan ,  Sunil Kumar C R ,  Vikas J

IPC: G09G5/00

CPC classification number: G09G5/006 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2330/021 ,  G09G2330/028 ,  G09G2370/08 ,  G09G2370/10 ,  G09G2370/12 ,  H04L25/0272

Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.

公开(公告)号：US10924305B2

公开(公告)日：2021-02-16

申请号：US16305116

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： Aruna Kumar ,  Anoop Karunan ,  Ganesh Balamurugan ,  Prakash Radhakrishnan

IPC: H04L25/02 ,  H04L25/03 ,  H04L1/24 ,  H04L7/10 ,  H04L25/08 ,  H04N21/4363

Abstract: Disclosed herein are devices and methods to facilitate compensating for intra-pair skew in a high-definition multimedia interface (HDMI) system. One or more skew training pattern may be transmitted on a signal line including a differential pair. Acknowledgment of receiving the skew training pattern may be received on a display data channel (DDC) associated with HDMI system. The skew training pattern may be used to ascertain and compensate for intra-pair skew.

公开(公告)号：US09653040B2

公开(公告)日：2017-05-16

申请号：US15359401

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Aruna Kumar ,  Prakash K. Radhakrishnan ,  Pravas Pradhan ,  Sunil Kumar C R ,  Vikas J

IPC: G09G5/00

CPC classification number: G09G5/006 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2330/021 ,  G09G2330/028 ,  G09G2370/08 ,  G09G2370/10 ,  G09G2370/12 ,  H04L25/0272

Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.

公开(公告)号：US09977477B2

公开(公告)日：2018-05-22

申请号：US14497476

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Sunil Kumar C. R. ,  Aruna Kumar ,  Prakash K. Radhakrishnan

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/266 ,  G06F1/26 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3293 ,  G06F1/3296 ,  G06F15/163

Abstract: In an embodiment, processor includes at least one logic circuit to generate information to be output from the processor; an input/output (IO) interface circuit coupled to the at least one logic circuit to receive and transmit the information; a voltage regulator to provide an operating voltage to the IO interface circuit; and a controller to control the voltage regulator to provide the operating voltage at an adjusted level from a nominal operating voltage based on a process variation of at least a portion of a die including the IO interface circuit. Other embodiments are described and claimed.

公开(公告)号：US20160091941A1

公开(公告)日：2016-03-31

申请号：US14497476

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Sunil Kumar C.R. ,  Aruna Kumar ,  Prakash K. Radhakrishnan

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/266 ,  G06F1/26 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3293 ,  G06F1/3296 ,  G06F15/163

Abstract: In an embodiment, processor includes at least one logic circuit to generate information to be output from the processor; an input/output (IO) interface circuit coupled to the at least one logic circuit to receive and transmit the information; a voltage regulator to provide an operating voltage to the IO interface circuit; and a controller to control the voltage regulator to provide the operating voltage at an adjusted level from a nominal operating voltage based on a process variation of at least a portion of a die including the IO interface circuit. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个逻辑电路以产生要从处理器输出的信息; 耦合到所述至少一个逻辑电路以接收和发送所述信息的输入/输出（IO）接口电路; 电压调节器，用于向IO接口电路提供工作电压; 以及控制器，用于控制所述电压调节器，以基于包括所述IO接口电路的管芯的至少一部分的工艺变化，将所述工作电压提供在来自标称工作电压的调整水平。 描述和要求保护其他实施例。