公开(公告)号：US20220199615A1

公开(公告)日：2022-06-23

申请号：US17133024

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Avyaya JAYANTHINARASIMHAM ,  Brian GREENE ,  Suresh Vishwanath

IPC: H01L27/07 ,  H01L27/088 ,  H01L29/861 ,  H01L29/78 ,  H01L29/06

Abstract: Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.

公开(公告)号：US20220415881A1

公开(公告)日：2022-12-29

申请号：US17357754

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Rui MA ,  Kalyan KOLLURU ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Chung-Hsun LIN

IPC: H01L27/02

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

公开(公告)号：US20220415925A1

公开(公告)日：2022-12-29

申请号：US17358329

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Nicholas THOMSON ,  Kalyan KOLLURU ,  Ayan KAR ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Lin HU ,  Chung-Hsun LIN

IPC: H01L27/12 ,  H01L27/02

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

公开(公告)号：US20210305436A1

公开(公告)日：2021-09-30

申请号：US16830112

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

IPC: H01L29/93 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20230317808A1

公开(公告)日：2023-10-05

申请号：US17700002

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Clifford ONG ,  Sukru YEMENICIOGLU ,  Tahir GHANI ,  Brian GREENE

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.

公开(公告)号：US20220416022A1

公开(公告)日：2022-12-29

申请号：US17357767

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Nicholas THOMSON ,  Kalyan KOLLURU ,  Ayan KAR ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Lin HU ,  Chung-Hsun LIN ,  Sabih OMAR

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/12

Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

公开(公告)号：US20220102385A1

公开(公告)日：2022-03-31

申请号：US17033418

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Avyaya JAYANTHINARASIMHAM ,  Ayan KAR ,  Benjamin ORR ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kalyan KOLLURU ,  Kevin FISCHER ,  Lin HU ,  Nathan JACK ,  Nicholas THOMSON ,  Rishabh MEHANDRU ,  Rui MA ,  Sabih OMAR

IPC: H01L27/12

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

公开(公告)号：US20220344519A1

公开(公告)日：2022-10-27

申请号：US17860056

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20220199610A1

公开(公告)日：2022-06-23

申请号：US17131616

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Daniel SCHULMAN ,  William HSU ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kevin FISCHER

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/87

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.