公开(公告)号：US20220102385A1

公开(公告)日：2022-03-31

申请号：US17033418

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Avyaya JAYANTHINARASIMHAM ,  Ayan KAR ,  Benjamin ORR ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kalyan KOLLURU ,  Kevin FISCHER ,  Lin HU ,  Nathan JACK ,  Nicholas THOMSON ,  Rishabh MEHANDRU ,  Rui MA ,  Sabih OMAR

IPC: H01L27/12

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

公开(公告)号：US20220415780A1

公开(公告)日：2022-12-29

申请号：US17356056

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： William HSU ,  Biswajeet GUHA ,  Mohit K. HARAN ,  Vadym KAPINUS ,  Robert BIGWOOD ,  Nidhi KHANDELWAL ,  Henning HAFFNER ,  Kevin FISCHER

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234

Abstract: Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

公开(公告)号：US20230197779A1

公开(公告)日：2023-06-22

申请号：US17556602

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Marni NABORS ,  Mauro J. KOBRINSKY ,  Conor P. PULS ,  Kevin FISCHER ,  Curtis TSAI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L23/481

Abstract: Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.

公开(公告)号：US20220199610A1

公开(公告)日：2022-06-23

申请号：US17131616

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Daniel SCHULMAN ,  William HSU ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kevin FISCHER

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/87

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.