公开(公告)号：US20230401109A1

公开(公告)日：2023-12-14

申请号：US18237860

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Te Khac MA ,  Surekha PERI ,  Pravin PATHAK ,  James CLEE ,  An YAN ,  Steven POLLOCK ,  Bruce RICHARDSON ,  Vijaya Bhaskar KOMMINENI ,  Abhinandan GUJJAR

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5038

Abstract: Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).

公开(公告)号：US20220214973A1

公开(公告)日：2022-07-07

申请号：US17707010

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Bruce RICHARDSON ,  Niall D. MCDONNELL ,  Subhiksha RAVISUNDAR

IPC: G06F12/0891 ,  G06F12/0842 ,  G06F12/0808 ,  G06F9/38

Abstract: Examples described herein relate to a device issuing a single command to request invalidation of multiple cache lines associated with a memory address range in a cache device. In some examples, the cache device is associated with the processor. In some examples, the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU).

公开(公告)号：US20240121194A1

公开(公告)日：2024-04-11

申请号：US18392028

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Bruce RICHARDSON ,  Te MA

IPC: H04L47/125 ,  H04L47/30 ,  H04L47/625

CPC classification number: H04L47/125 ,  H04L47/30 ,  H04L47/6255

Abstract: Methods, apparatus, and computer programs are disclosed for buffer management in load balancing. In one embodiment, a method is disclosed to comprise providing a set of buffers by a storage of a load balancer to store packets to be distributed by the load balancer, and distributing the packets by the load balancer to a set of cores of a computer processor to be processed by the set of cores. The method further comprises responsive to buffer utilization in the storage over a first threshold, obtaining by circuitry of the load balancer, from top of a memory stack coupled to the storage, additional buffers to store the packets to be distributed and responsive to buffer utilization in the storage below a second threshold, returning by the circuitry of the load balancer, available buffers in the storage to the top of the memory stack.

公开(公告)号：US20230035142A1

公开(公告)日：2023-02-02

申请号：US17966441

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  David HUNT ,  Kevin LAATZ ,  Anatoly BURAKOV ,  Bruce RICHARDSON ,  Conor WALSH ,  John J. BROWNE

IPC: G06F9/50

Abstract: A method is described. The method includes polling a queue a plurality of times over a plurality of intervals, where, the queue feeds work items to a processor. The method includes determining, from the polling, respective work item flow metrics for the plurality of intervals. The method includes determining a processor's performance setting based on the plurality of respective work item flow metrics.

公开(公告)号：US20220107838A1

公开(公告)日：2022-04-07

申请号：US17644117

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Bruce RICHARDSON ,  Rahul SHAH ,  Pravin PATHAK ,  Rashmi SHETTY

IPC: G06F9/48

Abstract: Examples relate to an apparatus, device, method, and computer program for processing a sequence of units of data, and of a computer program comprising such an apparatus or device. The apparatus comprises processing circuitry configured to obtain the sequence of units of data, obtain tokens indicating a readiness of a plurality of worker threads being executed on the processing circuitry, and process sub-sequences of the sequence of units of data by selecting, by a queue management circuitry of the processing circuitry, a worker thread from the plurality of worker threads based on the obtained tokens indicating the readiness, providing, by the queue management circuitry, a lock to a queue associated with the worker thread, the lock being associated with a resource comprising a sub-sequence of the sequence of units of data, obtaining, by the queue management circuitry, the lock from the worker thread after the worker thread has at least partially processed the sub-sequence of units of data stored in the resource, and proceeding with the next sub-sequence after the lock has been obtained.

公开(公告)号：US20190075063A1

公开(公告)日：2019-03-07

申请号：US16177262

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Bruce RICHARDSON ,  John MANGAN ,  Harry VAN HAAREN ,  Ciara LOFTUS ,  Brian A. KEATING

IPC: H04L12/931 ,  H04L12/861 ,  G06F9/54 ,  G06F13/10

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

公开(公告)号：US20190205149A1

公开(公告)日：2019-07-04

申请号：US16299914

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Fan ZHANG ,  Bruce RICHARDSON

IPC: G06F9/455 ,  G06F12/1027 ,  G06F9/30

CPC classification number: G06F9/45545 ,  G06F9/30181 ,  G06F9/4555 ,  G06F12/1027

Abstract: Examples include a processor including fetch circuitry to fetch a guest physical address translation instruction having a format with fields to specify at least an opcode and locations of a source vector and a destination vector, decode circuitry to decode the fetched guest physical address translation instruction, and execution circuitry to execute the decoded guest physical address translation instruction. Execution of the decoded guest physical address translation instruction includes comparing guest physical addresses of the source vector with base and end addresses of a selected memory region, masking a guest physical address of the source vector if the guest physical address is in the selected memory region, translating the masked guest physical addresses into host addresses, and storing the host addresses into the destination vector.