公开(公告)号：US20230101725A1

公开(公告)日：2023-03-30

申请号：US17485167

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Mauro J. KOBRINSKY ,  Gilbert DEWEY ,  Chi-hing CHOI ,  Harold W. Kennel ,  Brian J. KRIST ,  Ashkar ALIYARUKUNJU ,  Cory BOMBERGER ,  Rushabh SHAH ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Chanaka MUNASINGHE ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.

公开(公告)号：US20220399373A1

公开(公告)日：2022-12-15

申请号：US17348000

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka MUNASINGHE ,  Makram ABD EL QADER ,  Marie CONTE ,  Saurabh MORARKA ,  Elliot N. TAN ,  Krishna GANESAN ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84

Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.