公开(公告)号：US20220406646A1

公开(公告)日：2022-12-22

申请号：US17351803

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Vijay Saradhi Mangu ,  David Meyaard ,  Randy Koval ,  Krishna Parat

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/311

Abstract: An embodiment of a memory device may comprise a vertical channel, a first memory cell formed on the vertical channel, a first wordline coupled to the first memory cell, a second memory cell formed on the vertical channel immediately above the first memory cell, a second wordline coupled to the second memory cell, and an airgap disposed between the first wordline and the second wordline. Other embodiments are disclosed and claimed.

公开(公告)号：US12167592B2

公开(公告)日：2024-12-10

申请号：US17442582

申请日：2019-06-10

Applicant: INTEL CORPORATION

Inventor： Nanda Kumar Chakravarthi ,  David Meyaard ,  Abhinav Tripathi ,  Liu Liu

IPC: H01L27/11524 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35

Abstract: Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.

公开(公告)号：US20220399057A1

公开(公告)日：2022-12-15

申请号：US17343584

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Chang Wan Ha ,  Deepak Thimmegowda ,  Hoon Koh ,  Richard M. Gularte ,  Liu Liu ,  David Meyaard ,  Ahsanur Rahman

IPC: G11C16/04

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

公开(公告)号：US20200152650A1

公开(公告)日：2020-05-14

申请号：US16184641

申请日：2018-11-08

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen Jungroth ,  Khaled Hasnat ,  David Meyaard ,  Surendranath C. Eruvuru

IPC: H01L27/11556 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11519

Abstract: Embodiments of the present disclosure are directed towards a memory device with a split staircase, in accordance with some embodiments. In one embodiment, the memory device includes one or more pillars disposed in a die, and a plurality of wordlines formed in a stack of multiple tiers and coupled with the one or more pillars. At least some of the wordlines are split across the tiers into at least first and second portions. Respective ends of at least some wordlines of at least one of the first or second portions, at a location of the split, are exposed to provide electrical coupling with other components of the device. Other embodiments may be described and/or claimed.