公开(公告)号：US20220188016A1

公开(公告)日：2022-06-16

申请号：US17558353

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Virendra Vikramsinh Adsure ,  Taeyoung Kim ,  Chia-Hung S. Kuo ,  Deepak Gandiga Shivakumar ,  Amir Ali Radjai ,  Deepak Samuel Kirubakaran ,  Jianfang Zhu ,  Ivan Chen

IPC: G06F3/06

Abstract: An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.

公开(公告)号：US20210011853A1

公开(公告)日：2021-01-14

申请号：US16939158

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Cristiano J. Ferreira ,  Bo Qiu ,  Ajit Krisshna Nandyal Lakshman ,  Nikhil Talpallikar ,  Deepak Gandiga Shivakumar ,  Brandt M. Guttridge ,  Kim Pallister ,  Frank J. Soqui ,  Anand Srivatsa ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jonathan Kennedy

IPC: G06F12/10 ,  G06F12/0875 ,  G06F12/0811 ,  G06T1/60

Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.

公开(公告)号：US11893379B2

公开(公告)日：2024-02-06

申请号：US16995934

申请日：2020-08-18

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Deepak Gandiga Shivakumar ,  Dan Williams ,  Tiffany Kasanicky ,  Krzysztof Rusocki ,  Nicholas Moulin ,  Mohan J. Kumar

IPC: G06F8/654 ,  G06F8/656 ,  G06F9/4401 ,  G06F9/48

CPC classification number: G06F8/654 ,  G06F8/656 ,  G06F9/4401 ,  G06F9/4881

Abstract: Systems, apparatuses and methods may provide for technology that exchanges activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information. The technology also conducts a runtime upgrade of the device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system.

公开(公告)号：US20230086149A1

公开(公告)日：2023-03-23

申请号：US17483491

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Chia-Hung S. Kuo ,  Deepak Gandiga Shivakumar ,  Anoop Mukker ,  Arik Gihon ,  Zvika Greenfield ,  Asaf Rubinstein ,  Leo Aqrabawi

IPC: G06F12/0804 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3287

Abstract: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.

公开(公告)号：US10725929B2

公开(公告)日：2020-07-28

申请号：US15483741

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Cristiano J. Ferreira ,  Bo Qiu ,  Ajit Krisshna Nandyal Lakshman ,  Nikhil Talpallikar ,  Deepak Gandiga Shivakumar ,  Brandt M. Guttridge ,  Kim Pallister ,  Frank J. Soqui ,  Anand Srivatsa ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jonathan Kennedy

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/10 ,  G06F12/0875 ,  G06F12/0811 ,  G06T1/60 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/109

Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.

公开(公告)号：US12248356B2

公开(公告)日：2025-03-11

申请号：US17359403

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Virendra Vikramsinh Adsure ,  Chia-Hung S. Kuo ,  Robert J. Royer, Jr. ,  Deepak Gandiga Shivakumar

IPC: G06F1/3293

Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.

公开(公告)号：US20220171551A1

公开(公告)日：2022-06-02

申请号：US17673162

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Virendra Vikramsinh Adsure ,  Deepak Gandiga Shivakumar ,  Robert Royer, JR.

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods may provide for optimizing the available memory in a power conscious compute platform. For example, a semiconductor apparatus includes logic to communicate with a system memory to divide a plurality of memory channels into functional channels and performance channels. The functional channels are in an active power state during a boot process and the performance channels are in an idle power state during the boot process. The semiconductor apparatus includes logic to track memory usage and bring the performance channels out of the idle power state and into the active power state in response to the tracked memory usage.

公开(公告)号：US20210357204A1

公开(公告)日：2021-11-18

申请号：US16995934

申请日：2020-08-18

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Deepak Gandiga Shivakumar ,  Dan Williams ,  Tiffany Kasanicky ,  Krzysztof Rusocki ,  Nicholas Moulin ,  Mohan J. Kumar

IPC: G06F8/654 ,  G06F9/48 ,  G06F9/4401 ,  G06F8/656

Abstract: Systems, apparatuses and methods may provide for technology that exchanges activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information. The technology also conducts a runtime upgrade of the device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system.

公开(公告)号：US20180293173A1

公开(公告)日：2018-10-11

申请号：US15483741

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Cristiano J. Ferreira ,  Bo Qiu ,  Ajit Krisshna Nandyal Lakshman ,  Nikhil Talpallikar ,  Deepak Gandiga Shivakumar ,  Brandt M. Guttridge ,  Kim Pallister ,  Frank J. Soqui ,  Anand Srivatsa ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jonathan Kennedy

IPC: G06F12/10

Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.