公开(公告)号：US20240222441A1

公开(公告)日：2024-07-04

申请号：US18091197

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Carl Naylor ,  Chelsey Dorow ,  Chia-Ching Lin ,  Dominique Adams ,  Kevin O'Brien ,  Matthew Metz ,  Scott Clendenning ,  Sudarat Lee ,  Tristan Tronic ,  Uygar Avci

IPC: H01L29/40 ,  H01L21/04 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/44 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/043 ,  H01L21/044 ,  H01L21/28264 ,  H01L21/32136 ,  H01L21/44 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/454 ,  H01L29/78648 ,  H01L29/4908

Abstract: Devices, transistor structures, systems, and techniques, are described herein related to selective gate oxide formation on 2D materials for transistor devices. A transistor structure includes a gate dielectric structure on a 2D semiconductor material layer, and source and drain structures in contact with the gate dielectric structure and on the 2D semiconductor material layer. The source and drain structures include a metal material or metal nitride material and the gate dielectric structure includes an oxide of the metal material or metal nitride material.

公开(公告)号：US20250112155A1

公开(公告)日：2025-04-03

申请号：US18374532

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Scott Clendenning ,  Feras Eid ,  Robert Jordan ,  Wenhao Li ,  Jiun-Ruey Chen ,  Tayseer Mahdi ,  Carlos Felipe Bedoya Arroyave ,  Shashi Bhushan Sinha ,  Anandi Roy ,  Tristan Tronic ,  Dominique Adams ,  William Brezinski ,  Richard Vreeland ,  Thomas Sounart ,  Brian Barley ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/48 ,  H01L23/498 ,  H01L23/528

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.

公开(公告)号：US20240222485A1

公开(公告)日：2024-07-04

申请号：US18091209

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Tristan Tronic ,  Chelsey Dorow ,  Kevin O?Brien ,  Uygar Avci ,  Carl H. Naylor ,  Chia-Ching Lin ,  Dominique Adams ,  Matthew Metz ,  Ande Kitamura ,  Scott B. Clendenning

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/26 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/26 ,  H01L29/42392 ,  H01L29/66969

Abstract: A transistor structure includes a stack of nanoribbons coupling source and drain terminals. The nanoribbons may each include a pair of crystalline interface layers and a channel layer between the interface layers. The channel layers may be a molecular monolayer, including a metal and a chalcogen, with a thickness of less than 1 nm. The channel layers may be substantially monocrystalline, and the interface layers may be lattice matched to the channel layers. The channel layers may be epitaxially grown over the lattice-matched interface layers. The crystalline interface layers may be grown over sacrificial layers when forming the stack of nanoribbons.