公开(公告)号：US20170162676A1

公开(公告)日：2017-06-08

申请号：US15434981

申请日：2017-02-16

Applicant: Intel Corporation

Inventor： Annalisa CAPPELLANI ,  Stephen M. CEA ,  Tahir GHANI ,  Harry GOMEZ ,  Jack T. KAVALIEROS ,  Patrick H. KEYS ,  Seiyon KIM ,  Kelin J. KUHN ,  Aaron D. LILAK ,  Rafael RIOS ,  Mayank SAHNI

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US20190157411A1

公开(公告)日：2019-05-23

申请号：US16254489

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Annalisa CAPPELLANI ,  Abhijit Jayant PETHE ,  Tahir GHANI ,  Harry GOMEZ

IPC: H01L29/423 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/84 ,  H01L29/78 ,  H01L29/417 ,  H01L29/40 ,  H01L29/786 ,  H01L29/775 ,  H01L29/08

Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.

公开(公告)号：US20210210385A1

公开(公告)日：2021-07-08

申请号：US17211757

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Abhijit Jayant PETHE ,  Tahir GHANI ,  Mark BOHR ,  Clair WEBB ,  Harry GOMEZ ,  Annalisa CAPPELLANI

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

公开(公告)号：US20190115257A1

公开(公告)日：2019-04-18

申请号：US16219795

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Abhijit Jayant PETHE ,  Tahir GHANI ,  Mark BOHR ,  Clair WEBB ,  Harry GOMEZ ,  Annalisa CAPPELLANI

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L23/522 ,  H01L23/532

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.