公开(公告)号：US20170133462A1

公开(公告)日：2017-05-11

申请号：US15410649

申请日：2017-01-19

申请人： Intel Corporation

发明人： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  B82Y10/00 ,  H01L27/12

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20170162676A1

公开(公告)日：2017-06-08

申请号：US15434981

申请日：2017-02-16

申请人： Intel Corporation

发明人： Annalisa CAPPELLANI ,  Stephen M. CEA ,  Tahir GHANI ,  Harry GOMEZ ,  Jack T. KAVALIEROS ,  Patrick H. KEYS ,  Seiyon KIM ,  Kelin J. KUHN ,  Aaron D. LILAK ,  Rafael RIOS ,  Mayank SAHNI

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US20190157411A1

公开(公告)日：2019-05-23

申请号：US16254489

申请日：2019-01-22

申请人： Intel Corporation

发明人： Annalisa CAPPELLANI ,  Abhijit Jayant PETHE ,  Tahir GHANI ,  Harry GOMEZ

IPC分类号： H01L29/423 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/84 ,  H01L29/78 ,  H01L29/417 ,  H01L29/40 ,  H01L29/786 ,  H01L29/775 ,  H01L29/08

摘要： Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.

公开(公告)号：US20210210385A1

公开(公告)日：2021-07-08

申请号：US17211757

申请日：2021-03-24

申请人： Intel Corporation

发明人： Abhijit Jayant PETHE ,  Tahir GHANI ,  Mark BOHR ,  Clair WEBB ,  Harry GOMEZ ,  Annalisa CAPPELLANI

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

摘要： Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

公开(公告)号：US20200227520A1

公开(公告)日：2020-07-16

申请号：US16831692

申请日：2020-03-26

申请人： Intel Corporation

发明人： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC分类号： H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20200152797A1

公开(公告)日：2020-05-14

申请号：US16740089

申请日：2020-01-10

申请人： Intel Corporation

发明人： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L21/268 ,  H01L29/78

摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US20190115257A1

公开(公告)日：2019-04-18

申请号：US16219795

申请日：2018-12-13

申请人： Intel Corporation

发明人： Abhijit Jayant PETHE ,  Tahir GHANI ,  Mark BOHR ,  Clair WEBB ,  Harry GOMEZ ,  Annalisa CAPPELLANI

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L23/522 ,  H01L23/532

摘要： Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

公开(公告)号：US20150303258A1

公开(公告)日：2015-10-22

申请号：US14789856

申请日：2015-07-01

申请人： Intel Corporation

发明人： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. Cea ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L27/12 ,  H01L29/165 ,  H01L27/092 ,  H01L29/16

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。