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公开(公告)号:US10229981B2
公开(公告)日:2019-03-12
申请号:US15335281
申请日:2016-10-26
Applicant: Intel Corporation
Inventor: Annalisa Cappellani , Abhijit Jayant Pethe , Tahir Ghani , Harry Gomez
IPC: H01L29/06 , H01L29/423 , H01L21/84 , H01L21/306 , H01L29/66 , H01L29/08 , B82Y10/00 , H01L29/775 , H01L29/78 , H01L29/786 , H01L29/40 , H01L29/417 , H01L21/762
Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
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公开(公告)号:US10192783B2
公开(公告)日:2019-01-29
申请号:US15266819
申请日:2016-09-15
Applicant: Intel Corporation
Inventor: Abhijit Jayant Pethe , Tahir Ghani , Mark Bohr , Clair Webb , Harry Gomez , Annalisa Cappellani
IPC: H01L21/70 , H01L21/768 , H01L29/66 , H01L29/78 , H01L21/28 , H01L21/311 , H01L23/522 , H01L23/532
Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
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公开(公告)号:US11004739B2
公开(公告)日:2021-05-11
申请号:US16219795
申请日:2018-12-13
Applicant: Intel Corporation
Inventor: Abhijit Jayant Pethe , Tahir Ghani , Mark Bohr , Clair Webb , Harry Gomez , Annalisa Cappellani
IPC: H01L21/768 , H01L29/78 , H01L29/66 , H01L21/28 , H01L21/311 , H01L23/522 , H01L23/532
Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
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公开(公告)号:US12278144B2
公开(公告)日:2025-04-15
申请号:US17211757
申请日:2021-03-24
Applicant: Intel Corporation
Inventor: Abhijit Jayant Pethe , Tahir Ghani , Mark Bohr , Clair Webb , Harry Gomez , Annalisa Cappellani
IPC: H01L21/768 , H01L21/28 , H01L21/311 , H01L23/522 , H01L23/532 , H01L29/66 , H01L29/78
Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
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公开(公告)号:US09978636B2
公开(公告)日:2018-05-22
申请号:US15219138
申请日:2016-07-25
Applicant: Intel Corporation
Inventor: Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Harry Gomez
IPC: H01L21/762 , H01L29/78 , H01L29/06 , H01L27/12 , H01L27/088
CPC classification number: H01L21/76237 , H01L21/76232 , H01L27/088 , H01L27/1207 , H01L29/0638 , H01L29/0653 , H01L29/7851
Abstract: Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
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公开(公告)号:US10026829B2
公开(公告)日:2018-07-17
申请号:US15434981
申请日:2017-02-16
Applicant: Intel Corporation
Inventor: Annalisa Cappellani , Stephen M. Cea , Tahir Ghani , Harry Gomez , Jack T. Kavalieros , Patrick H. Keys , Seiyon Kim , Kelin J. Kuhn , Aaron D. Lilak , Rafael Rios , Mayank Sahni
IPC: H01L29/66 , H01L29/78 , H01L21/762 , H01L29/06 , H01L29/775 , H01L27/12 , B82Y10/00 , H01L29/423
Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
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