公开(公告)号：US20240020093A1

公开(公告)日：2024-01-18

申请号：US18477716

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Deepak Dasalukunte ,  Renzhi Liu ,  Hechen Wang ,  Brent Carlton

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.

公开(公告)号：US20230161559A1

公开(公告)日：2023-05-25

申请号：US18159220

申请日：2023-01-25

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F7/544 ,  G06F7/48 ,  H03M1/78 ,  H03M1/46

CPC classification number: G06F7/5443 ,  G06F7/4824 ,  H03M1/78 ,  H03M1/462

Abstract: Systems, apparatuses and methods may provide for technology that conducts, by a differential signal path, signed multiply-accumulate (MAC) operations on first analog signals and multibit weight data stored in the differential signal path, and outputs, by the differential signal path, second analog signals based on the signed MAC operations.

公开(公告)号：US20220406392A1

公开(公告)日：2022-12-22

申请号：US17353493

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Renzhi Liu ,  Deepak Dasalukunte

IPC: G11C27/02 ,  G06N3/063

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

公开(公告)号：US20210150328A1

公开(公告)日：2021-05-20

申请号：US17159312

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Hechen Wang

IPC: G06N3/063 ,  G06N3/04 ,  H04L12/713 ,  H04L12/933

Abstract: Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.

公开(公告)号：US20210034947A1

公开(公告)日：2021-02-04

申请号：US17075527

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  David Israel Gonzalez Aguirre

IPC: G06N3/04 ,  H03L7/089 ,  H03L7/099 ,  G06F1/06

Abstract: Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

公开(公告)号：US12254399B2

公开(公告)日：2025-03-18

申请号：US17159312

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Hechen Wang

IPC: G06N3/065 ,  G06N3/047 ,  H04L45/586 ,  H04L49/109

Abstract: Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.

公开(公告)号：US12131245B2

公开(公告)日：2024-10-29

申请号：US17075527

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  David Israel Gonzalez Aguirre

IPC: G06N3/04 ,  G06F1/06 ,  H03L7/089 ,  H03L7/099 ,  G11C11/412

CPC classification number: G06N3/04 ,  G06F1/06 ,  H03L7/0891 ,  H03L7/0995 ,  G11C11/412

Abstract: Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

公开(公告)号：US20230289066A1

公开(公告)日：2023-09-14

申请号：US18187950

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F3/06 ,  G06N3/0464 ,  G06F7/544

CPC classification number: G06F3/0613 ,  G06N3/0464 ,  G06F3/0659 ,  G06F3/0673 ,  G06F7/5443

Abstract: Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.

公开(公告)号：US20230229504A1

公开(公告)日：2023-07-20

申请号：US17937248

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F9/50 ,  G06F7/544 ,  H03M1/18

CPC classification number: G06F9/5027 ,  G06F7/5443 ,  H03M1/18

Abstract: Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.

公开(公告)号：US10969431B1

公开(公告)日：2021-04-06

申请号：US16724576

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Richard William Dorrance ,  Andrey Vladimirovich Belogolovy ,  Xue Zhang ,  Hechen Wang

IPC: G06F17/50 ,  G01R31/00 ,  G01R31/3177 ,  G06F30/398 ,  G06F30/3308 ,  G06F30/20

Abstract: A semiconductor package comprises a controlled voltage domain (CVD) and a master voltage domain (MVD). The MVD comprises an error-tolerance control (ETC) circuit. A basic execution block in the CVD generates a basic output value, based on at least two input values. A test execution block in the CVD generates a test digital root, based on digital roots of the input values. A digital root comparator in the CVD determines whether a digital root of the basic output value matches the test digital root. An error reporter in the CVD sends an error report to the ETC circuit in response to a determination that the digital roots do not match. The ETC may automatically adjust at least one power characteristic of the CVD, based on the error report. Other embodiments are described and claimed.