公开(公告)号：US20180174890A1

公开(公告)日：2018-06-21

申请号：US15897935

申请日：2018-02-15

Applicant: Intel Corporation

Inventor： James Mathew ,  Yunjun Ho ,  Zhiqiang Xie ,  Hyun Sik Kim

IPC: H01L21/762 ,  H01L27/115 ,  H01L25/00 ,  H01L25/065 ,  H01L21/66 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

公开(公告)号：US10453829B2

公开(公告)日：2019-10-22

申请号：US15625350

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Merri Lyn Carlson ,  Hongbin Zhu ,  Gordon A. Haller ,  James E. Davis ,  Kevin G. Duesman ,  James Mathew ,  Michael P. Violette

IPC: H01L27/11556 ,  H01L25/10 ,  H01L27/11529 ,  H01L27/11548

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

公开(公告)号：US10784144B2

公开(公告)日：2020-09-22

申请号：US15897935

申请日：2018-02-15

Applicant: Intel Corporation

Inventor： James Mathew ,  Yunjun Ho ,  Zhiqiang Xie ,  Hyun Sik Kim

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/02 ,  H01L25/00 ,  H01L25/065 ,  H01L27/115 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/11582

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

公开(公告)号：US20180366453A1

公开(公告)日：2018-12-20

申请号：US15625350

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Merri Lyn Carlson ,  Hongbin Zhu ,  Gordon A. Haller ,  James E. Davis ,  Kevin G. Duesman ,  James Mathew ,  Michael P. Violette

IPC: H01L25/10 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L25/105 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

公开(公告)号：US09935000B2

公开(公告)日：2018-04-03

申请号：US15056620

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： James Mathew ,  Yunjun Ho ,  Zhiqiang Xie ,  Hyun Sik Kim

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/02 ,  H01L25/00 ,  H01L25/065 ,  H01L27/115 ,  H01L21/66

CPC classification number: H01L21/76232 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/8221 ,  H01L21/823481 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/115 ,  H01L28/00

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.

公开(公告)号：US20170250108A1

公开(公告)日：2017-08-31

申请号：US15056620

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： James Mathew ,  Yunjun Ho ,  Zhiqiang Xie ,  Hyun Sik Kim

IPC: H01L21/762 ,  H01L21/66 ,  H01L25/065 ,  H01L27/115 ,  H01L21/02 ,  H01L25/00

CPC classification number: H01L21/76232 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/8221 ,  H01L21/823481 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/115 ,  H01L28/00

Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.