公开(公告)号：US20240145420A1

公开(公告)日：2024-05-02

申请号：US17975654

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Kooi Chi OOI ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG

IPC: H01L23/00

CPC classification number: H01L24/26 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13101 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13188 ,  H01L2224/1413 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2732 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/30051 ,  H01L2224/3016 ,  H01L2224/32227 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/83193 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/01087 ,  H01L2924/0133 ,  H01L2924/0543 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.

公开(公告)号：US20240145365A1

公开(公告)日：2024-05-02

申请号：US18050519

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Kooi Chi OOI ,  Jackson Chung Peng KONG

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49833

Abstract: A device is provided, including a dielectric layer, a plurality of first conductive segments within the dielectric layer and spaced apart from each other by respective first spacings, and a plurality of second conductive segments within the dielectric layer and spaced apart from each other by respective second spacings. The plurality of second conductive segments may be over and spaced apart from the plurality of first conductive segments by the dielectric layer. A respective one of the first conductive segments may at least partially extend across a corresponding one of the second spacings, and a respective one of the second conductive segments may at least partially extend across a corresponding one of the first spacings.

公开(公告)号：US20220406753A1

公开(公告)日：2022-12-22

申请号：US17348802

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Yang Liang POH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.

公开(公告)号：US20220068764A1

公开(公告)日：2022-03-03

申请号：US17089750

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L25/16 ,  H01L23/00

Abstract: According to various examples, a device is described. The device may include an interposer. The device may also include a plurality of first through-silicon-vias disposed in the interposer, wherein the plurality of first through-silicon-vias have a first diameter. The device may also include a plurality of second through-silicon-vias disposed in the interposer, wherein the plurality of second through-silicon-vias have a second diameter larger than the first via diameter. The device may also include a first recess in the interposer positioned at bottom ends of the plurality of second through-silicon-vias.

公开(公告)号：US20240136269A1

公开(公告)日：2024-04-25

申请号：US17968830

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/49833 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L25/0655 ,  H01L25/162 ,  H01L25/18 ,  H01L25/50 ,  H01L24/32

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.

公开(公告)号：US20240071934A1

公开(公告)日：2024-02-29

申请号：US17894200

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Seok Ling LIM

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1436 ,  H01L2924/3511

Abstract: The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.

公开(公告)号：US20240071856A1

公开(公告)日：2024-02-29

申请号：US17895102

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/367 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L23/3736

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a substrate and a first die with first and second opposing surfaces. The first die may be coupled to the substrate at the first surface. At least one first trench may extend partially through the first die from the second surface. A stiffener may be attached to the substrate. The stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. A thermally conductive layer may be positioned between the stiffener and the first die. The conductive layer at least partially fills the at least one first trench.

公开(公告)号：US20220077113A1

公开(公告)日：2022-03-10

申请号：US17089741

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM

IPC: H01L25/065 ,  H01L27/06 ,  H01L23/367 ,  H01L23/538 ,  H01L21/50

Abstract: A chip package includes a substrate; a first chip including thermal VIAs, wherein the first chip is coupled to the substrate; a conductive frame at least partially surrounding the first chip and coupled to the substrate, wherein the first chip and the conductive frame have a height that is substantially the same, wherein an exposed substrate surface is covered in a layer of encapsulation material having the same height; a second chip positioned on a first portion the first chip surface in such a way to expose at least a portion of the first chip surface, wherein the at least one exposed portion includes thermal VIAs; and at least one conductive plate positioned on the at least one exposed portion, wherein the conductive plate is coupled to the conductive frame and the thermal VIAs of the first chip.

公开(公告)号：US20220068821A1

公开(公告)日：2022-03-03

申请号：US17090919

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/552 ,  H01L21/48

Abstract: A device is provided, including a package substrate, a first interposer including a plurality of first vias extending through the first interposer, and a second interposer including a plurality of second vias extending through the second interposer. The first interposer and the second interposer may be arranged on the package substrate and may be spaced apart from each other.

公开(公告)号：US20240234283A9

公开(公告)日：2024-07-11

申请号：US17968830

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/49833 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L25/0655 ,  H01L25/162 ,  H01L25/18 ,  H01L25/50 ,  H01L24/32

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.