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    Multi-wavelength laser
    1.
    发明授权
    Multi-wavelength laser 有权

    公开(公告)号：US10727640B2

    公开(公告)日：2020-07-28

    申请号：US16233687

    申请日：2018-12-27

    Applicant: INTEL CORPORATION

    Inventor： Jie Sun ,  Haisheng Rong ,  Ranjeet Kumar

    IPC: H04J14/02 ,  H01S3/067 ,  H01S3/00 ,  H01S3/08 ,  G02B6/12 ,  H04B10/50

    Abstract: There is disclosed in one example a communication system, including: a data transmission interface; and a wavelength division multiplexing (WDM) silicon laser source to provide modulated data on a carrier laser via the data transmission interface, the WDM laser including a single laser cavity to generate an internally multiplexed multi-wavelength laser, the single laser cavity including a filter having a first grating period to generate a first wavelength and a second grating period to generate a second wavelength, the second grating period superimposed on the first grating period.

    MULTI-WAVELENGTH LASER
    4.
    发明申请
    MULTI-WAVELENGTH LASER 审中-公开

    公开(公告)号：US20190140415A1

    公开(公告)日：2019-05-09

    申请号：US16233687

    申请日：2018-12-27

    Applicant: INTEL CORPORATION

    Inventor： Jie Sun ,  Haisheng Rong ,  Ranjeet Kumar

    IPC: H01S3/067 ,  H04J14/02 ,  G02B6/12 ,  H01S3/08 ,  H01S3/00

    Abstract: There is disclosed in one example a communication system, including: a data transmission interface; and a wavelength division multiplexing (WDM) silicon laser source to provide modulated data on a carrier laser via the data transmission interface, the WDM laser including a single laser cavity to generate an internally multiplexed multi-wavelength laser, the single laser cavity including a filter having a first grating period to generate a first wavelength and a second grating period to generate a second wavelength, the second grating period superimposed on the first grating period.

    THREE DIMENSIONAL MEMORY STRUCTURE
    5.
    发明申请
    THREE DIMENSIONAL MEMORY STRUCTURE 审中-公开
    三维存储器结构

    公开(公告)号：US20150333085A1

    公开(公告)日：2015-11-19

    申请号：US14813398

    申请日：2015-07-30

    Applicant: Intel Corporation

    Inventor： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

    IPC: H01L27/115 ,  H01L29/04 ,  G11C16/06 ,  H01L29/16

    CPC classification number: H01L27/11582 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

    Abstract translation: 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。

    Three dimensional memory structure
    6.
    发明授权
    Three dimensional memory structure 有权
    三维记忆结构

    公开(公告)号：US09129859B2

    公开(公告)日：2015-09-08

    申请号：US13786925

    申请日：2013-03-06

    Applicant: Intel Corporation

    Inventor： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

    IPC: H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11582 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

    Abstract translation: 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。

    On-chip optical isolator
    7.
    发明授权
    On-chip optical isolator 有权

    公开(公告)号：US10466515B2

    公开(公告)日：2019-11-05

    申请号：US15071105

    申请日：2016-03-15

    Applicant: Intel Corporation

    Inventor： John Heck ,  David N. Hutchison ,  Jie Sun ,  Haisheng Rong ,  Woosung Kim

    IPC: G02B6/13 ,  G02B6/12 ,  G02B6/27 ,  G02B6/293 ,  G02F1/095 ,  H01S5/00 ,  G02B6/132 ,  G02F1/00

    Abstract: Embodiments herein relate to photonic integrated circuits with an on-chip optical isolator. A photonic transmitter chip may include a laser and an on-chip isolator optically coupled with the laser that includes an optical waveguide having a section coupled with a magneto-optic liquid phase epitaxy grown garnet film. In some embodiments, a cladding may be coupled with the garnet film, the on-chip isolator may be arranged in a Mach-Zehnder interferometer configuration, the waveguide may include one or more polarization rotators, and/or the garnet film may be formed of a material from a rare-earth garnet family. Other embodiments may be described and/or claimed.

    MANUFACTURING A TOUCH SENSOR
    8.
    发明申请
    MANUFACTURING A TOUCH SENSOR 审中-公开

    公开(公告)号：US20190278429A1

    公开(公告)日：2019-09-12

    申请号：US16462399

    申请日：2016-12-19

    Applicant: INTEL CORPORATION

    Inventor： Dong Yeung Kwak ,  Ramon C. Cancel Olmo ,  Jue Li ,  Jie Sun

    IPC: G06F3/044 ,  B41J3/407

    Abstract: An electronic device (400) for manufacturing a touch sensor is described. The electronic device (400) includes a printer (418) to print a first pattern and a second pattern on a first side of a first substrate (202). The first pattern is parallel to movement of a print head (206). The first pattern and the second pattern are perpendicular to each other. The electronic device (400) also includes a rotator (420) to rotate the first substrate (202) so that the printer (418) is to print the second pattern parallel to the movement of the print head (206).

    Wide-angle, aliasing-free beam steering using aperiodic emitter arrays
    9.
    发明授权
    Wide-angle, aliasing-free beam steering using aperiodic emitter arrays 有权

    公开(公告)号：US10203452B2

    公开(公告)日：2019-02-12

    申请号：US15395874

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Jie Sun ,  Haisheng Rong ,  Jonathan K. Doylend

    IPC: G02B6/12 ,  G01S17/10 ,  G01S17/42 ,  G01S17/89 ,  G01S7/481 ,  G02B6/34

    Abstract: A transmission circuit includes an array of subarrays of emitters with quasi-periodic spacing. A first subarray of emitters emits a source signal, and a second subarray of emitters emits the source signal. The first and second subarrays are separated by a subarray spacing that quasi-periodic, wherein the spacing between different subarrays is different. The quasi-periodic subarray spacing is to cause constructive interference of a main lobe of the emissions from the subarrays, and to cause non-constructive interference of sidelobes of the emissions. The spacing between emitters in the subarrays can vary from one subarray to another.

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