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    DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT
    3.
    发明申请
    DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT 审中-公开
    下游设备服务延迟报告用于电源管理

    公开(公告)号：US20150257101A1

    公开(公告)日：2015-09-10

    申请号：US14595085

    申请日：2015-01-12

    Applicant: Intel Corporation

    Inventor： Jaya L. Jeyaseelan ,  Jim Walsh ,  Robert E. Gough ,  Barnes Cooper ,  Neil W. Songer

    IPC: H04W52/02 ,  H04L12/26

    CPC classification number: H04W52/0225 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  G06F13/4282 ,  H04L43/0858 ,  Y02D10/151 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/23

    Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.

    Abstract translation: 对于一个公开的实施例，可以识别对于下游设备的至少一部分从第一状态到第二不同状态的转变。 第一和第二状态可以对应于与下游设备的至少一部分的活动有关的不同级别。 响应于所识别的一个或多个上游设备的转换，至少部分地基于服务等待时间来对应于服务等待时间的数据可被发送到上游设备以管理电力。 还公开了其他实施例。

    Downstream device service latency reporting for power management
    5.
    发明授权
    Downstream device service latency reporting for power management 有权

    公开(公告)号：US10182398B2

    公开(公告)日：2019-01-15

    申请号：US15453208

    申请日：2017-03-08

    Applicant: Intel Corporation

    Inventor： Jaya L. Jeyaseelan ,  Jim Walsh ,  Robert E. Gough ,  Barnes Cooper ,  Neil W. Songer

    IPC: H04W52/02 ,  G06F13/42 ,  G06F1/32 ,  H04L12/26 ,  G06F1/20

    Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.

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