公开(公告)号：US20220216065A1

公开(公告)日：2022-07-07

申请号：US17701367

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Marie KRYSAK ,  James M. BLACKWELL ,  Florian GSTREIN ,  Kent N. FRASURE

IPC: H01L21/311 ,  G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US20190043731A1

公开(公告)日：2019-02-07

申请号：US16075555

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Marie KRYSAK ,  James M. BLACKWELL ,  Florian GSTREIN ,  Kent N. FRASURE

IPC: H01L21/311 ,  G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US20180130707A1

公开(公告)日：2018-05-10

申请号：US15573108

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Scott B. CLENDENNING ,  Martin M. MITAN ,  Timothy E. GLASSMAN ,  Flavio GRIGGIO ,  Grant M. KLOSTER ,  Kent N. FRASURE ,  Florian GSTREIN ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76876 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2221/1063

Abstract: Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.