公开(公告)号：US11211324B2

公开(公告)日：2021-12-28

申请号：US16574308

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20240113194A1

公开(公告)日：2024-04-04

申请号：US17957580

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Mekha George ,  Seda Cekli ,  Kilhyun Bang ,  Krishna Ganesan

IPC: H01L29/423 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/31116 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

Abstract: Materials and techniques for recessing heterogenous materials in integrated circuit (IC) dies. A first etch may reveal a surface at a desired depth, and a second etch may remove material laterally to reveal sidewalls down to the desired depth of the recess. The first etch may be a cyclical etch, and the second etch may be a continuous etch. The first and second etches may occur in a same chamber. The first and second etches may each be selective to materials with similarities. An IC die may have different, substantially coplanar materials at a recessed surface between and below sidewalls of another material. The recess may have squared profile. The recess may be over transistor structures.

公开(公告)号：US11652045B2

公开(公告)日：2023-05-16

申请号：US17511656

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/5329

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20210082805A1

公开(公告)日：2021-03-18

申请号：US16574308

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.