公开(公告)号：US20160034224A1

公开(公告)日：2016-02-04

申请号：US14815508

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0643 ,  G06F3/0679 ,  G06F9/5061 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  Y02D10/13

Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与非易失性存储器上的数据结构的瞬态和持久状态之间就地改变相关的方法和装置。 在一个实施例中，控制器逻辑引起一个或多个非易失性存储器件的第一部分在持久状态和瞬态之间的状态的改变，而不移动存储在一个或多个非易失性存储器件的第一部分中的数据 存储设备。 还公开并要求保护其他实施例。

公开(公告)号：US12086446B2

公开(公告)日：2024-09-10

申请号：US17031721

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Thomas E. Willis ,  Durgesh Srivastava ,  Marcelo Cintra ,  Bassam N. Coury ,  Donald L. Faw ,  Francois Dugast

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067

Abstract: Examples herein relate to a system capable of coupling to a remote memory pool, the system comprising: a memory controller and an interface to a connection, the interface coupled to the memory controller. In some examples, the interface is to translate a format of a memory access request to a format accepted by the memory controller and the memory controller is to provide the translated memory access request in a format accepted by a media. In some examples, a controller is to measure a number of addressable regions that are least accessed and cause at least one of the least accessed regions to be evicted to a local or remote memory device with relatively higher latency. In some examples, a remote access manager is to: determine if a region of addressable memory associated with a memory address for an access request is stored in the memory; based on the region of addressable memory associated with the memory address being stored in the memory, determine if a sub-region of addressable memory associated with the memory address is available for access from the memory, wherein the sub-region comprises less than an entirety of the region; and based on the sub-region of addressable memory being available for access from the memory, provide a physical address for use to access data from the sub-region in the memory and copy the data to the cache.

公开(公告)号：US12192023B2

公开(公告)日：2025-01-07

申请号：US17103602

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

Abstract: Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.

公开(公告)号：US12132581B2

公开(公告)日：2024-10-29

申请号：US17103802

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

CPC classification number: H04L12/1868 ,  G06F12/0238 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/4059 ,  H04L12/5601 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  G06F2213/28 ,  H04L2012/562

Abstract: Examples described herein includes an apparatus comprising: a network interface configured to: receive a request to copy data from a local memory to a remote memory; based on a configuration that the network interface is to manage a cache store the data into the cache and record that the data is stored in the cache. In some examples, store the data in the cache comprises store most recently evicted data from the local memory into the cache. In some examples, the network interface is to store data evicted from the local memory that is not stored into the cache into one or more remote memories.

公开(公告)号：US09335944B2

公开(公告)日：2016-05-10

申请号：US14815508

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/50 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0643 ,  G06F3/0679 ,  G06F9/5061 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  Y02D10/13

Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.

公开(公告)号：US09128824B2

公开(公告)日：2015-09-08

申请号：US13726303

申请日：2012-12-24

Applicant: Intel Corporation

Inventor： Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/50

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0643 ,  G06F3/0679 ,  G06F9/5061 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  Y02D10/13

Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与非易失性存储器上的数据结构的瞬态和持久状态之间就地改变相关的方法和装置。 在一个实施例中，控制器逻辑引起一个或多个非易失性存储器件的第一部分在持久状态和瞬态之间的状态的改变，而不移动存储在一个或多个非易失性存储器件的第一部分中的数据 存储设备。 还公开并要求保护其他实施例。