公开(公告)号：US20210057381A1

公开(公告)日：2021-02-25

申请号：US16548255

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Xavier F. BRUN ,  Kaizad MISTRY ,  Paul R. START ,  Nisha ANANTHAKRISHNAN ,  Yawei LIANG ,  Jigneshkumar P. PATEL ,  Sairam AGRAHARAM ,  Liwei WANG

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

公开(公告)号：US20230197574A1

公开(公告)日：2023-06-22

申请号：US18111329

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5385 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/09 ,  H01L24/83 ,  H01L25/16 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16237

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20210272881A1

公开(公告)日：2021-09-02

申请号：US17323840

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20250046680A1

公开(公告)日：2025-02-06

申请号：US18921373

申请日：2024-10-21

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20190043778A1

公开(公告)日：2019-02-07

申请号：US16061324

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Zhizhong TANG ,  Shinobu KOURAKATA ,  Kazuo OGATA ,  Paul R. START ,  Syadwad JIAN ,  William Nicholas LABANOK ,  Wei HU ,  Peng LI ,  Douglas R. YOUNG ,  Gregory S. CONSTABLE ,  John J. Beatty ,  Pardeep K. BHATTI ,  Luke J. GARNER ,  Aravindha R. ANTONISWAMY

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments are generally directed to a swaging process for complex integrated heat spreaders. An embodiment of an integrated heat spreader includes components, each of the components including one or more swage points; and a multiple swage joints, each swage joint including a swage pin joining two or more components, wherein components are joined into a single integrated heat spreader unit by the swage joints.