公开(公告)号：US11652061B2

公开(公告)日：2023-05-16

申请号：US16442801

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Shenavia S. Howell ,  John J. Beatty ,  Raymond A. Krick ,  Suzana Prstic

IPC: H01L23/538 ,  H01L23/488 ,  H01L21/78 ,  H01L23/532

CPC classification number: H01L23/5386 ,  H01L21/7806 ,  H01L23/488 ,  H01L23/53242 ,  H01L23/53257

Abstract: Embodiments may relate to a microelectronic package that includes a die and a backside metallization (BSM) layer positioned on the face of the die. The BSM layer may include a feature that indicates that the BSM layer was formed on the face of the die by a masked deposition technique. Other embodiments may be described or claimed.

公开(公告)号：US11676873B2

公开(公告)日：2023-06-13

申请号：US16614765

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Dinesh Padmanabhan Ramalekshmi Thanu ,  Hemanth K. Dhavaleswarapu ,  Venkata Suresh Guthikonda ,  John J. Beatty ,  Yonghao An ,  Marco Aurelio Cartas Ayala ,  Luke J. Garner ,  Peng Li

IPC: H01L23/16 ,  H01L21/52 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/16 ,  H01L21/52 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5383 ,  H01L25/0655 ,  H01L25/165 ,  H01L24/32 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

公开(公告)号：US20190043778A1

公开(公告)日：2019-02-07

申请号：US16061324

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Zhizhong TANG ,  Shinobu KOURAKATA ,  Kazuo OGATA ,  Paul R. START ,  Syadwad JIAN ,  William Nicholas LABANOK ,  Wei HU ,  Peng LI ,  Douglas R. YOUNG ,  Gregory S. CONSTABLE ,  John J. Beatty ,  Pardeep K. BHATTI ,  Luke J. GARNER ,  Aravindha R. ANTONISWAMY

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments are generally directed to a swaging process for complex integrated heat spreaders. An embodiment of an integrated heat spreader includes components, each of the components including one or more swage points; and a multiple swage joints, each swage joint including a swage pin joining two or more components, wherein components are joined into a single integrated heat spreader unit by the swage joints.

公开(公告)号：US20180350712A1

公开(公告)日：2018-12-06

申请号：US15610327

申请日：2017-05-31

Applicant: INTEL CORPORATION

Inventor： Dinesh P. R. Thanu ,  Hemanth K. Dhavaleswarapu ,  John J. Beatty ,  Sachin Deshmukh

IPC: H01L23/36 ,  H01L23/498 ,  H01L21/48

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, a plurality of microelectronic devices attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one of the plurality of microelectronic devices and attached to the microelectronic substrate, and at least one offset spacer attached between the microelectronic substrate and the heat dissipation device to control the bondline thickness between the heat dissipation device and at least one of the plurality of microelectronic devices.

公开(公告)号：US11652018B2

公开(公告)日：2023-05-16

申请号：US17343565

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Dinesh P. R. Thanu ,  Hemanth K. Dhavaleswarapu ,  John J. Beatty ,  Syadwad Jain ,  Nachiket R. Raravikar

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/81

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.

公开(公告)号：US11328978B2

公开(公告)日：2022-05-10

申请号：US16639545

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna M. Swan ,  Sergio Chan Arguedas ,  John J. Beatty

IPC: H01L23/367 ,  H01L21/48 ,  H01L49/02 ,  H01L23/00 ,  H01L23/10

Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

公开(公告)号：US20210305118A1

公开(公告)日：2021-09-30

申请号：US17343565

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Dinesh P. R. Thanu ,  Hemanth K. Dhavaleswarapu ,  John J. Beatty ,  Syadwad Jain ,  Nachiket R. Raravikar

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.

公开(公告)号：US20190067153A1

公开(公告)日：2019-02-28

申请号：US15689463

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Dinesh P. R. Thanu ,  Hemanth K. Dhavaleswarapu ,  John J. Beatty ,  Syadwad Jain ,  Nachiket R. Raravikar

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.

公开(公告)号：US11776869B2

公开(公告)日：2023-10-03

申请号：US17718031

申请日：2022-04-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna M. Swan ,  Sergio Chan Arguedas ,  John J. Beatty

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/10 ,  H01L49/02 ,  H01L23/42

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L28/40 ,  H01L23/10 ,  H01L23/42 ,  H01L24/30 ,  H01L24/32

Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

公开(公告)号：US11328979B2

公开(公告)日：2022-05-10

申请号：US16639956

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Dinesh Padmanabhan Ramalekshmi Thanu ,  Sergio Chan Arguedas ,  Johanna M. Swan ,  John J. Beatty

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.