公开(公告)号：US09645939B2

公开(公告)日：2017-05-09

申请号：US14752783

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M Sankaran ,  Sanjay Kumar

IPC: G06F12/0891 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/214 ,  G06F2212/7201

Abstract: Hardware apparatuses and methods for distributed durable and atomic transactions in non-volatile memory are described. In one embodiment, a hardware apparatus includes a hardware processor, a plurality of hardware memory controllers for each of a plurality of non-volatile data storage devices, and a plurality of staging buffers with a staging buffer for each of the plurality of hardware memory controllers, wherein each of the plurality of hardware memory controllers are to: write data of a data set that is to be written to the plurality of non-volatile data storage devices to their staging buffer, send confirmation to the hardware processor that the data is written to their staging buffer, and write the data from their staging buffer to their non-volatile data storage device on receipt of a commit command.

公开(公告)号：US10509729B2

公开(公告)日：2019-12-17

申请号：US14994393

申请日：2016-01-13

Applicant: Intel Corporation

Inventor： Rajesh M Sankaran ,  Randolph L Campbell ,  Prashant Sethi ,  David J Harriman

IPC: G06F12/10 ,  G06F12/1027 ,  G06F9/455 ,  G06F12/1009 ,  G06F12/1081

Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.

公开(公告)号：US08949571B2

公开(公告)日：2015-02-03

申请号：US14070561

申请日：2013-11-03

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Dion Rodgers ,  Rajesh M Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G11C15/00 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US10713195B2

公开(公告)日：2020-07-14

申请号：US14997478

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Jr-Shian Tsai ,  Ravi L Sahita ,  Mesut A Ergin ,  Rajesh M Sankaran ,  Gilbert Neiger ,  Jun Nakajima ,  Edwin Verplanke ,  Barry E Huntley ,  Tsung-Yuan C Tai

IPC: G06F13/24 ,  G06F9/455

Abstract: Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.

公开(公告)号：US20160092223A1

公开(公告)日：2016-03-31

申请号：US14498178

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Cheng Wang ,  Youfeng Wu ,  Rajesh M Sankaran

IPC: G06F9/30 ,  G06F12/08 ,  G06F9/38

Abstract: A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed.

Abstract translation: 一方面的处理器包括解码单元，用于解码持久存储栏指令。 处理器还包括与解码单元耦合的存储器子系统模块。 存储器子系统模块响应于永久存储围栏指令，确保在持久存储指令的数据被持久地存储在永久存储器中之前，与永久存储围栏指令相对应的给定数据被永久地存储在持久存储器中。 随后的存储指令发生在原始程序顺序中的持久存储栏指令之后。 还公开了其它处理器，方法，系统和制品。