公开(公告)号：US12119057B2

公开(公告)日：2024-10-15

申请号：US17540884

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Rouhollah Mousavi Iraei ,  Mini Goel ,  Raymond Zeng ,  Hemant P. Rao

IPC: G11C13/04 ,  G06F3/06 ,  G11C13/00

CPC classification number: G11C13/004 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0679 ,  G11C13/0004 ,  G11C13/0023

Abstract: In one embodiment, a state is reach from a memory cell comprising a phase change material (PM) region and a select device (SD) region by: ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage, ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell, detecting a snap in the memory cell while ramping the voltage applied to the second address line, and determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

公开(公告)号：US20230267988A1

公开(公告)日：2023-08-24

申请号：US17679971

申请日：2022-02-24

Applicant: Intel Corporation

Inventor： Lu Liu ,  Hemant P. Rao ,  Phoebe P. Yeoh ,  Raymond Zeng

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4074

CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4074

Abstract: A method, apparatus and system. The apparatus includes one or more processors to: determine that a memory operation including one of a write operation or a read operation is to be implemented on a memory cell of a memory array, the memory operation having a duration equal to a latency window and being based on a voltage change across the memory cell equal to a target memory window; and in response to a determination that the memory operation is to be implemented, cause, during the latency window, an application to the memory cell of a current pulse amplitude profile progressively decreasing between and including at least four current pulse amplitudes.

公开(公告)号：US20230064007A1

公开(公告)日：2023-03-02

申请号：US17408352

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Rouhollah Mousavi Iraei ,  Kiran Pangal ,  Saad P. Monasa ,  Mini Goel ,  Raymond Zeng ,  Hemant P. Rao

IPC: G11C13/00

Abstract: In one embodiment, a state is encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

公开(公告)号：US20200160908A1

公开(公告)日：2020-05-21

申请号：US16685719

申请日：2019-11-15

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

公开(公告)号：US10482960B2

公开(公告)日：2019-11-19

申请号：US15046339

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.

公开(公告)号：US12249372B2

公开(公告)日：2025-03-11

申请号：US17408352

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Rouhollah Mousavi Iraei ,  Kiran Pangal ,  Saad P. Monasa ,  Mini Goel ,  Raymond Zeng ,  Hemant P. Rao

IPC: G11C16/04 ,  G11C13/00 ,  H10B63/00

Abstract: A state may be encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

公开(公告)号：US20230260573A1

公开(公告)日：2023-08-17

申请号：US17671091

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Rouhollah Mousavi Iraei ,  Mini Goel ,  Hemant P. Rao ,  Raymond Zeng

IPC: G11C11/56 ,  G11C8/06

CPC classification number: G11C11/5628 ,  G11C8/06 ,  G11C11/5642 ,  G11C11/5678

Abstract: A memory device comprising a plurality of memory cells, a memory cell of the plurality of memory cells comprising a phase change material (PM) region and a select device (SD) region in series with the PM region; a first address line and a second address line coupled to the memory cell; and memory controller circuitry to interface with the first address line and the second address line, the memory controller circuitry to encode a state in the memory cell by applying, through the first address line and second address line, a current spike and a programming pulse to the memory cell to cause the PM region to be placed into an amorphous state and the SD region of the memory cell to be placed into a high threshold voltage state.

公开(公告)号：US11024380B2

公开(公告)日：2021-06-01

申请号：US16685719

申请日：2019-11-15

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

公开(公告)号：US20230178148A1

公开(公告)日：2023-06-08

申请号：US17540884

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Rouhollah Mousavi Iraei ,  Mini Goel ,  Raymond Zeng ,  Hemant P. Rao

IPC: G11C13/00 ,  G06F3/06

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0023 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: In one embodiment, a state is reach from a memory cell comprising a phase change material (PM) region and a select device (SD) region by: ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage, ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell, detecting a snap in the memory cell while ramping the voltage applied to the second address line, and determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

公开(公告)号：US20170236580A1

公开(公告)日：2017-08-17

申请号：US15046339

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.