公开(公告)号：US11024380B2

公开(公告)日：2021-06-01

申请号：US16685719

申请日：2019-11-15

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

公开(公告)号：US10438659B2

公开(公告)日：2019-10-08

申请号：US16037255

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US20170236580A1

公开(公告)日：2017-08-17

申请号：US15046339

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.

公开(公告)号：US20190013071A1

公开(公告)日：2019-01-10

申请号：US16037255

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US20200160908A1

公开(公告)日：2020-05-21

申请号：US16685719

申请日：2019-11-15

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

公开(公告)号：US10482960B2

公开(公告)日：2019-11-19

申请号：US15046339

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Daniel Chu ,  Kiran Pangal ,  Mase Taub ,  Sandeep Guliani ,  Raymond Zeng

IPC: G11C13/00

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.

公开(公告)号：US10032508B1

公开(公告)日：2018-07-24

申请号：US15396224

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US20180190353A1

公开(公告)日：2018-07-05

申请号：US15396224

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/12 ,  G11C2213/71

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US10553286B2

公开(公告)日：2020-02-04

申请号：US16147422

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Daniel Chu ,  Shravya Gottipati

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.

公开(公告)号：US20190043585A1

公开(公告)日：2019-02-07

申请号：US16147422

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Daniel Chu ,  Shravya Gottipati

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/0061 ,  G11C16/0433 ,  G11C16/32 ,  G11C16/3427 ,  G11C2013/0092

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.