公开(公告)号：US20220238383A1

公开(公告)日：2022-07-28

申请号：US17720150

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20200066907A1

公开(公告)日：2020-02-27

申请号：US16317708

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

公开(公告)号：US20200273752A1

公开(公告)日：2020-08-27

申请号：US15930700

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20190245098A1

公开(公告)日：2019-08-08

申请号：US16344226

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02236 ,  H01L21/02241 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

公开(公告)号：US20180323260A1

公开(公告)日：2018-11-08

申请号：US15773536

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Hsu-Yu CHANG ,  Neville L. DIAS ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

公开(公告)号：US20250098275A1

公开(公告)日：2025-03-20

申请号：US18967144

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20200066897A1

公开(公告)日：2020-02-27

申请号：US16318108

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Joodong PARK ,  Chen-Guan LEE ,  Chia-Hong JAN ,  Everett S. CASSIDY-COMFORT

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.

公开(公告)号：US20200066712A1

公开(公告)日：2020-02-27

申请号：US16318107

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Joodong PARK ,  Chen-Guan LEE ,  Chia-Hong JAN

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

公开(公告)号：US20210090956A1

公开(公告)日：2021-03-25

申请号：US17112959

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20190278022A1

公开(公告)日：2019-09-12

申请号：US16462077

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Chia-Hong JAN ,  Walid HAFEZ ,  Neville DIAS ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/134 ,  G02B6/136

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.