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    METHODS AND APPARATUS TO REDUCE DISPLAY CONNECTION LATENCY
    1.
    发明申请
    METHODS AND APPARATUS TO REDUCE DISPLAY CONNECTION LATENCY 有权

    公开(公告)号：US20220291733A1

    公开(公告)日：2022-09-15

    申请号：US17831173

    申请日：2022-06-02

    Applicant: Intel Corporation

    Inventor： Lakshminarayana Pappu ,  Nausheen Ansari ,  Todd Witter

    IPC: G06F1/26 ,  G09G3/20

    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to reduce display connection latency. An example apparatus includes interface circuitry to: detect when a display is plugged into a port; and notify processor circuitry of the detection. In response to the notification, the processor circuitry of the example apparatus moves discrete circuitry into a high power state. The example apparatus also includes discrete circuitry to, while in the high power state, identify the display.

    Isochronous agent data pinning in a multi-level memory system
    2.
    发明授权
    Isochronous agent data pinning in a multi-level memory system 有权
    多级存储器系统中的同步代理数据固定

    公开(公告)号：US09542336B2

    公开(公告)日：2017-01-10

    申请号：US14133097

    申请日：2013-12-18

    Applicant: INTEL CORPORATION

    Inventor： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

    IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12

    CPC classification number: G06F12/126

    Abstract: A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

    Abstract translation: 处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。 此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。

    DYNAMIC SLEEP FOR A DISPLAY PANEL
    4.
    发明申请
    DYNAMIC SLEEP FOR A DISPLAY PANEL 审中-公开

    公开(公告)号：US20190043415A1

    公开(公告)日：2019-02-07

    申请号：US16024587

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Vishal Sinha ,  Paul Diefenbaugh ,  Todd Witter ,  Jason Tanner ,  Arthur Runyan ,  Nausheen Ansari ,  Kathy Bui ,  Yifan Li

    IPC: G09G3/22 ,  G06F1/32

    Abstract: Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.

    SERIAL BUS DISPLAY PORT SOLUTION FOR DISCRETE GRAPHICS
    6.
    发明申请
    SERIAL BUS DISPLAY PORT SOLUTION FOR DISCRETE GRAPHICS 有权

    公开(公告)号：US20220068242A1

    公开(公告)日：2022-03-03

    申请号：US17003634

    申请日：2020-08-26

    Applicant: Intel Corporation

    Inventor： Patrick Maloney ,  Robert Johnston ,  Sindhu Amireddy ,  Todd Witter

    IPC: G09G5/36 ,  G06F13/42

    Abstract: Methods, systems and apparatuses may provide for a system memory, an external graphics source, and a host processor coupled to the system memory and the external graphics source. The host processor may include an integrated graphics source, an output port, a set of input pins, wherein the set if input pins are dedicated to the external graphics source, and a communication path between the set of input pins and the output port. In one example, the communication path bypasses the system memory and the integrated graphics source.

    DYNAMIC SLEEP FOR A DISPLAY PANEL
    7.
    发明申请
    DYNAMIC SLEEP FOR A DISPLAY PANEL 有权

    公开(公告)号：US20210090485A1

    公开(公告)日：2021-03-25

    申请号：US16866520

    申请日：2020-05-04

    Applicant: Intel Corporation

    Inventor： Vishal Sinha ,  Paul Diefenbaugh ,  Todd Witter ,  Jason Tanner ,  Arthur Runyan ,  Nausheen Ansari ,  Kathy Bui ,  Yifan Li

    IPC: G09G3/22 ,  G06F1/3237 ,  G06F1/3234 ,  G06F1/3206 ,  G09G3/20 ,  G06F3/041

    Abstract: Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.

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