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公开(公告)号:US20190043778A1
公开(公告)日:2019-02-07
申请号:US16061324
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Zhizhong TANG , Shinobu KOURAKATA , Kazuo OGATA , Paul R. START , Syadwad JIAN , William Nicholas LABANOK , Wei HU , Peng LI , Douglas R. YOUNG , Gregory S. CONSTABLE , John J. Beatty , Pardeep K. BHATTI , Luke J. GARNER , Aravindha R. ANTONISWAMY
IPC: H01L23/367 , H01L21/48 , H01L25/065
Abstract: Embodiments are generally directed to a swaging process for complex integrated heat spreaders. An embodiment of an integrated heat spreader includes components, each of the components including one or more swage points; and a multiple swage joints, each swage joint including a swage pin joining two or more components, wherein components are joined into a single integrated heat spreader unit by the swage joints.
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公开(公告)号:US20170179080A1
公开(公告)日:2017-06-22
申请号:US14975128
申请日:2015-12-18
Applicant: Intel Corporation
Inventor: Akshay MATHKAR , Nachiket Raghunath RARAVIKAR , Donald Tiendung TRAN , Jerry Lee JENSEN , Javier A. FALCON , William Nicholas LABANOK , Robert Leon SANKMAN , Robert Allen STINGEL
IPC: H01L25/065 , H01L23/29 , H05K1/02 , H01L21/56 , H01L25/00 , H05K1/11 , H01L23/498 , H01L21/48
CPC classification number: H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/293 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L25/105 , H01L25/50 , H01L2225/06548 , H01L2225/06555 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H05K1/0298 , H05K1/115
Abstract: Semiconductor package interposers having high-density and high-aspect ratio encapsulated interconnects, and semiconductor package assemblies incorporating such interposers, are described. In an example, a semiconductor package interposer includes several conductive interconnects encapsulated in a polymer substrate and having height dimensions greater than a cross-sectional dimension. The semiconductor package interposer may support a first semiconductor package above a second semiconductor package and may electrically connect die pins of the first semiconductor package to die pins of the second semiconductor package.
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