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公开(公告)号:US20190310964A1
公开(公告)日:2019-10-10
申请号:US16346842
申请日:2016-12-28
Applicant: INTEL CORPORATION
Inventor: Zhiyuan ZHANG , Xiangbin WU , Qianying ZHU , Xinxin ZHANG , Haitao JI , Yingzho SHE
IPC: G06F15/173 , G06F13/20 , G06F13/40
Abstract: Provided is an apparatus directing to a speculative read mechanism for a distributed storage system. The apparatus includes a remote direct memory access (RDMA) network interface card (RNIC) (100) for a server (250), wherein the RNIC (100) includes an onboard memory (105), a trigger control (120) and a port for connection of the RNIC (100) to a client (200). The onboard memory (105) is operable to provide a buffer (110) for storage of data from a distributed storage system for a read request from the client (200). The trigger control (120) includes a programmable trigger condition. The RNIC (100) is operable to support a speculative read of data in response to a read request snoop of a write of data to the onboard memory (105), and upon detecting the trigger condition, to provide the data in the buffer to the client (200).
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公开(公告)号:US20220343762A1
公开(公告)日:2022-10-27
申请号:US17762761
申请日:2019-12-27
Applicant: Intel Corporation
Inventor: Ignacio J. ALVAREZ , Cornelius BUERKLE , Haitao JI , Fei LI , Fabian OBORIL , Johannes QUAST , Kay-Ulrich SCHOLL , John Charles WEAST , Xiangbin WU , Xinxin ZHANG , Zhiyuan ZHANG , Qianying ZHU
IPC: G08G1/0968 , G06V20/58 , G08G1/01 , G08G1/0962
Abstract: One or more processors may be configured to determine one or more prospective routes of an ego vehicle being at least partially controlled by a human driver; receive first sensor data, representing one or more attributes of a second vehicle; determine a danger probability of the one or more prospective routes of the first vehicle using the at least the one or more attributes of the second vehicle from the first sensor data; and if each of the one or more prospective routes of the first vehicle has a danger probability outside of a predetermined range, send a signal representing a safety intervention. Whenever a safety intervention signal is sent, the one or more processors may be configured to increment or decrement a counter.
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公开(公告)号:US20220324467A1
公开(公告)日:2022-10-13
申请号:US17642739
申请日:2019-12-27
Applicant: Intel Corporation
Inventor: Ignacio J. ALVAREZ , Florian GEISSLER , Haitao JI , Fei LI , Fabian OBORIL , Rafael ROSALES , Kay-Ulrich SCHOLL , Xiangbin WU , Xinxin ZHANG , Zhiyuan ZHANG , Qianying ZHU
Abstract: A safety system (200) for a vehicle (100) is provided. The safety system (200) may include one or more processors (102). The one or more processors (102) may be configured to control a vehicle (100) to operate in accordance with the predefined stored driving model parameters, to detect vehicle operation data during the operation of the vehicle (100), to determine whether to change predefined driving model parameters based on the detected vehicle operation data and the driving model parameters, to change the driving model parameters to changed driving model parameters, and to control the vehicle (100) to operate in accordance with the changed driving model parameters.
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公开(公告)号:US20200159629A1
公开(公告)日:2020-05-21
申请号:US16616905
申请日:2017-06-30
Applicant: Intel Corporation
Inventor: Zhiyuan ZHANG , Xiangbin WU , Xinxin ZHANG , Qianying ZHU , Haitao JI , Yingzhe SHEN
Abstract: An embodiment of a memory apparatus may include a logger to log memory access data in persistent storage media, a log indexer communicatively coupled to the logger to index the memory access log data in an index table in a system memory, and a key compressor communicatively coupled to the log indexer to compress an index key for the index table. Other embodiments are disclosed and claimed.
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公开(公告)号:US20190332314A1
公开(公告)日:2019-10-31
申请号:US16465107
申请日:2016-12-29
Applicant: Intel Corporation
Inventor: Zhiyuan ZHANG , Xiangbin WU , Qianying ZHU , Xinxin ZHANG , Yingzhe SHEN , Haitao JI
IPC: G06F3/06
Abstract: Embodiments of the present disclosure provide devices, techniques, and configurations for network interface controllers (NICs) that log write packets received from a network in non-volatile random access memory (NVRAM). In one embodiment, a NIC includes a network interface to couple a host of the NIC to a network, a NVRAM, and a controller coupled with the network interface and the NVRAM, where the controller is to log write packets received at the network interface from the network in the NVRAM. Other embodiments may be described and/or claimed.
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