公开(公告)号：US20190310964A1

公开(公告)日：2019-10-10

申请号：US16346842

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Zhiyuan ZHANG ,  Xiangbin WU ,  Qianying ZHU ,  Xinxin ZHANG ,  Haitao JI ,  Yingzho SHE

IPC: G06F15/173 ,  G06F13/20 ,  G06F13/40

Abstract: Provided is an apparatus directing to a speculative read mechanism for a distributed storage system. The apparatus includes a remote direct memory access (RDMA) network interface card (RNIC) (100) for a server (250), wherein the RNIC (100) includes an onboard memory (105), a trigger control (120) and a port for connection of the RNIC (100) to a client (200). The onboard memory (105) is operable to provide a buffer (110) for storage of data from a distributed storage system for a read request from the client (200). The trigger control (120) includes a programmable trigger condition. The RNIC (100) is operable to support a speculative read of data in response to a read request snoop of a write of data to the onboard memory (105), and upon detecting the trigger condition, to provide the data in the buffer to the client (200).

公开(公告)号：US20220343762A1

公开(公告)日：2022-10-27

申请号：US17762761

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ignacio J. ALVAREZ ,  Cornelius BUERKLE ,  Haitao JI ,  Fei LI ,  Fabian OBORIL ,  Johannes QUAST ,  Kay-Ulrich SCHOLL ,  John Charles WEAST ,  Xiangbin WU ,  Xinxin ZHANG ,  Zhiyuan ZHANG ,  Qianying ZHU

IPC: G08G1/0968 ,  G06V20/58 ,  G08G1/01 ,  G08G1/0962

Abstract: One or more processors may be configured to determine one or more prospective routes of an ego vehicle being at least partially controlled by a human driver; receive first sensor data, representing one or more attributes of a second vehicle; determine a danger probability of the one or more prospective routes of the first vehicle using the at least the one or more attributes of the second vehicle from the first sensor data; and if each of the one or more prospective routes of the first vehicle has a danger probability outside of a predetermined range, send a signal representing a safety intervention. Whenever a safety intervention signal is sent, the one or more processors may be configured to increment or decrement a counter.

公开(公告)号：US20220324467A1

公开(公告)日：2022-10-13

申请号：US17642739

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ignacio J. ALVAREZ ,  Florian GEISSLER ,  Haitao JI ,  Fei LI ,  Fabian OBORIL ,  Rafael ROSALES ,  Kay-Ulrich SCHOLL ,  Xiangbin WU ,  Xinxin ZHANG ,  Zhiyuan ZHANG ,  Qianying ZHU

IPC: B60W50/00 ,  B60W60/00

Abstract: A safety system (200) for a vehicle (100) is provided. The safety system (200) may include one or more processors (102). The one or more processors (102) may be configured to control a vehicle (100) to operate in accordance with the predefined stored driving model parameters, to detect vehicle operation data during the operation of the vehicle (100), to determine whether to change predefined driving model parameters based on the detected vehicle operation data and the driving model parameters, to change the driving model parameters to changed driving model parameters, and to control the vehicle (100) to operate in accordance with the changed driving model parameters.

公开(公告)号：US20170039145A1

公开(公告)日：2017-02-09

申请号：US14911353

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： Xiangbin WU ,  Gansha WU

IPC: G06F12/14 ,  G06F12/0813 ,  H04L9/32 ,  H04L9/14 ,  H04L29/06

CPC classification number: G06F12/1408 ,  G06F12/0813 ,  G06F12/1466 ,  G06F15/17331 ,  G06F17/30902 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/60 ,  H04L9/14 ,  H04L9/3226 ,  H04L63/06 ,  H04L67/1097 ,  H04L67/2842 ,  H04L67/42

Abstract: Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a server apparatus may include memory; one or more processors; a network interface card to support remote memory direct access of the memory, by a client device, for a value of a key using an address that is a morph address of a physical address of a storage location of the memory having the value; and server side memcached logic operated by the one or more processors. Other embodiments may be described and/or claimed.

Abstract translation: 本文公开了与memcached系统相关联的装置，方法和存储介质。 在实施例中，服务器设备可以包括存储器; 一个或多个处理器; 网络接口卡，用于通过客户端设备支持远程存储器对存储器的存储器的物理地址的变形地址的地址作为密钥的值进行直接存取，该地址是具有该值的存储器的存储位置的物理地址; 和由一个或多个处理器操作的服务器端memcached逻辑。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20240346809A1

公开(公告)日：2024-10-17

申请号：US18574935

申请日：2022-01-07

Applicant: Intel Corporation

Inventor： Ping GUO ,  Mee Sim LAI ,  Kuan Heng LEE ,  Wee Hoo CHEAH ,  Jason GARCIA ,  Liang QIU ,  Peng WANG ,  Jiajie WU ,  Xiangbin WU

IPC: G06V10/776 ,  G06V10/70 ,  G06V10/77 ,  G06V10/774 ,  G06V10/82 ,  G06V20/40 ,  G09B19/00

CPC classification number: G06V10/776 ,  G06V10/768 ,  G06V10/7715 ,  G06V10/774 ,  G06V20/41 ,  G06V20/44 ,  G06V20/49 ,  G09B19/003 ,  G06V10/82

Abstract: The application provides an apparatus and a method for procedural video assessment. The apparatus includes: interface circuitry; and processor circuitry coupled to the interface circuitry and configured to: perform an action segmentation process for a procedural video received via the interface circuitry to obtain a plurality of action features associated with the procedure video; transform the plurality of action features into a plurality of action-procedure features based on an action-procedure relationship learning module for discovering a relationship between the plurality of action features and a plurality of scoring oriented procedures associated with the procedure video; and perform a procedure classification process to infer the plurality of scoring oriented procedures from the plurality of action-procedure features.

公开(公告)号：US20220333944A1

公开(公告)日：2022-10-20

申请号：US17763230

申请日：2019-12-27

Applicant: Intel Corporation ,  Mobileye Vision Technologies LTD.

Inventor： Yuqing HOU ,  Xiaolong LIU ,  Ignacio J. ALVAREZ ,  Xiangbin WU

IPC: G01C21/34 ,  G01C21/36

Abstract: Provided is a device and a method for route planning. The route planning device (100) may include a data interface (128) coupled to a road and traffic data source (160); a user interface (170) configured to display a map and receive a route planning request from a user, the route planning request including a line of interest on the map; a processor (110) coupled to the data interface (128) and the user interface (170). The processor (110) may be configured to identify the line of interest in response to the route planning request; acquire, via the data interface (128), road and traffic information associated with the line of interest from the road and traffic data source (160); and calculate, based on the acquired road and traffic information, a navigation route that matches or corresponds to the line of interest and meets or satisfies predefined road and traffic constraints.

公开(公告)号：US20200159629A1

公开(公告)日：2020-05-21

申请号：US16616905

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Zhiyuan ZHANG ,  Xiangbin WU ,  Xinxin ZHANG ,  Qianying ZHU ,  Haitao JI ,  Yingzhe SHEN

IPC: G06F11/14 ,  G06F12/16 ,  G06F17/40 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14

Abstract: An embodiment of a memory apparatus may include a logger to log memory access data in persistent storage media, a log indexer communicatively coupled to the logger to index the memory access log data in an index table in a system memory, and a key compressor communicatively coupled to the log indexer to compress an index key for the index table. Other embodiments are disclosed and claimed.

公开(公告)号：US20190332314A1

公开(公告)日：2019-10-31

申请号：US16465107

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zhiyuan ZHANG ,  Xiangbin WU ,  Qianying ZHU ,  Xinxin ZHANG ,  Yingzhe SHEN ,  Haitao JI

IPC: G06F3/06

Abstract: Embodiments of the present disclosure provide devices, techniques, and configurations for network interface controllers (NICs) that log write packets received from a network in non-volatile random access memory (NVRAM). In one embodiment, a NIC includes a network interface to couple a host of the NIC to a network, a NVRAM, and a controller coupled with the network interface and the NVRAM, where the controller is to log write packets received at the network interface from the network in the NVRAM. Other embodiments may be described and/or claimed.