公开(公告)号：US12057386B2

公开(公告)日：2024-08-06

申请号：US17024507

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Wei Qian ,  Cung Tran ,  Sungbong Park ,  John Heck ,  Mark Isenberger ,  Seth Slavin ,  Mengyuan Huang ,  Kelly Magruder ,  Harel Frish ,  Reece Defrees ,  Zhi Li

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L23/528

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

公开(公告)号：US12298560B2

公开(公告)日：2025-05-13

申请号：US17523668

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Olufemi I. Dosunmu ,  Zhi Li ,  Mengyuan Huang ,  Aliasghar Eftekhar

IPC: G02B6/136 ,  G02B6/12 ,  H01L31/0232 ,  H01L31/024 ,  H01L31/028 ,  H01L31/18

Abstract: In one embodiment, an apparatus includes a substrate, an oxide layer on the substrate, a silicon layer on the oxide layer, which includes a waveguide region and etched regions adjacent to the waveguide region, a germanium layer on the silicon layer and adjacent the waveguide region of the silicon layer, and a resistive element adjacent to the germanium layer to provide heat to the germanium layer in response to a current applied to the resistive element.

公开(公告)号：US20220416097A1

公开(公告)日：2022-12-29

申请号：US17358921

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： David Kohen ,  Kelly Magruder ,  Parastou Fakhimi ,  Zhi Li ,  Cung Tran ,  Wei Qian ,  Mark Isenberger ,  Mengyuan Huang ,  Harel Frish ,  Reece DeFrees ,  Ansheng Liu

IPC: H01L31/0232 ,  G02B6/12 ,  H01L31/105 ,  H01L31/107 ,  H01L31/18

Abstract: A photodetector structure over a partial length of a silicon waveguide structure within a photonic integrated circuit (PIC) chip. The photodetector structure is embedded within a cladding material surrounding the waveguide structure. The photodetector structure includes an absorption region, for example comprising Ge. A sidewall of the cladding material may be lined with a sacrificial spacer. After forming the absorption region, the sacrificial spacer may be removed and passivation material formed over a sidewall of the absorption region. Between the absorption region an impurity-doped portion of the waveguide structure there may be a carrier multiplication region, for example comprising crystalline silicon. If present, edge facets of the carrier multiplication region may be protected by a spacer material during the formation of an impurity-doped charge carrier layer. Occurrence of edge facets may be mitigated by embedding a portion of the photodetector structure with a thickness of the waveguide structure.

公开(公告)号：US20220107461A1

公开(公告)日：2022-04-07

申请号：US17523668

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Olufemi I. Dosunmu ,  Zhi Li ,  Mengyuan Huang ,  Aliasghar Eftekhar

IPC: G02B6/136 ,  G02B6/12 ,  H01L31/0232 ,  H01L31/024 ,  H01L31/028 ,  H01L31/18

Abstract: In one embodiment, an apparatus includes a substrate, an oxide layer on the substrate, a silicon layer on the oxide layer, which includes a waveguide region and etched regions adjacent to the waveguide region, a germanium layer on the silicon layer and adjacent the waveguide region of the silicon layer, and a resistive element adjacent to the germanium layer to provide heat to the germanium layer in response to a current applied to the resistive element.