公开(公告)号：US12294024B2

公开(公告)日：2025-05-06

申请号：US17660729

申请日：2022-04-26

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Masashi Tsubuku ,  Kentaro Miura ,  Akihiro Hanada ,  Takaya Tamaru

IPC: H01L29/66 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

公开(公告)号：US12108627B2

公开(公告)日：2024-10-01

申请号：US17533127

申请日：2021-11-23

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Kentaro Miura ,  Hajime Watakabe ,  Ryo Onodera

IPC: H01L27/32 ,  H01L51/56 ,  H10K59/121 ,  H10K59/126 ,  H10K71/00 ,  H01L27/12 ,  H01L29/786 ,  H10K59/12 ,  H10K59/123

CPC classification number: H10K59/1213 ,  H10K59/126 ,  H10K71/00 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/78675 ,  H01L29/7869 ,  H10K59/1201 ,  H10K59/123

Abstract: A display device includes a first transistor having a first semiconductor layer, in which a first source region includes a first region in contact with a first source electrode, and a first drain region includes a second region in contact with a first drain electrode. The first source and drain regions, the first region, and the second region each include a first impurity element. In a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region. A method of manufacturing a display device includes forming a first gate electrode and a light shielding layer on a first insulating layer, and forming a second semiconductor layer on the light shielding layer.

公开(公告)号：US12148840B2

公开(公告)日：2024-11-19

申请号：US17542515

申请日：2021-12-06

Applicant: Japan Display Inc.

Inventor： Kentaro Miura ,  Hajime Watakabe ,  Ryo Onodera

IPC: H01L29/786 ,  H01L29/66

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.

公开(公告)号：US12176438B2

公开(公告)日：2024-12-24

申请号：US17549882

申请日：2021-12-14

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Kentaro Miura ,  Toshinari Sasaki ,  Takeshi Sakai ,  Akihiro Hanada ,  Masashi Tsubuku

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.