公开(公告)号：US07689425B2

公开(公告)日：2010-03-30

申请号：US11153660

申请日：2005-06-15

Applicant: Do-Sung Kim ,  Dong-Soon Min ,  Kwan-Sik Yoo ,  Seung-Woo Chung ,  Jeong-Hun Lee

Inventor： Do-Sung Kim ,  Dong-Soon Min ,  Kwan-Sik Yoo ,  Seung-Woo Chung ,  Jeong-Hun Lee

IPC: G10L21/00

CPC classification number: G10L15/22 ,  H04M3/5166 ,  H04M2203/2011

Abstract: A QoS call routing system using a counselor and a speech recognition engine comprises a speech recognition engine for recognizing speech and outputting characters and speech recognition results; a first counselor group terminal for reproducing the client's speech file to a counselor of a first counselor group so that the counselor may recognize the speech when the speech recognition result by the speech recognition engine is less than a reference value; a second counselor group terminal for allowing a counselor of a second counselor group to hear the client's speech so that the counselor may recognize the speech when the recognition by the counselor of the first counselor group has failed; and an IVR server for controlling the engine and terminals to provide information to the client.

Abstract translation: 使用顾问和语音识别引擎的QoS呼叫路由系统包括用于识别语音并输出字符和语音识别结果的语音识别引擎; 第一顾问组终端，用于将顾客的语音文件再现给第一顾问组的顾问，使得当语音识别引擎的语音识别结果小于参考值时，辅导员可以识别语音; 第二辅导组织终端，允许第二顾问组的顾问听取客户的演讲，以便辅导员在第一顾问组的顾问的认可失败时可以承认该演讲; 以及用于控制引擎和终端以向客户端提供信息的IVR服​​务器。

公开(公告)号：US06833522B1

公开(公告)日：2004-12-21

申请号：US10781996

申请日：2004-02-19

Applicant: Kyung-Su Park ,  Chul-Gi Min ,  Jeong-Hun Lee

Inventor： Kyung-Su Park ,  Chul-Gi Min ,  Jeong-Hun Lee

IPC: H01H1370

CPC classification number: H01H3/125 ,  H01H2215/004

Abstract: A key switch device includes inner and outer link members connected to each other to mutually move in a scissors fashion, a key top having receiving portions for receiving the support protrusions provided at respective upper ends of the link members, a hollow elastic switch provided at an inner surface thereof with a downward protrusion for performing a switching operation in accordance with vertical movement of the key top, a support plate arranged beneath the key top, a membrane arranged on the support plate, and a mounting member arranged on the membrane, a central opening for receiving the elastic switch, and fitting holes allowing the cocking members to be fitted therein.

Abstract translation: 钥匙开关装置包括彼此连接的内部和外部连杆构件以剪刀的方式相互移动，键顶部具有用于接收设置在连杆构件的相应上端处的支撑突起的接收部分， 其内表面具有向下突起，用于根据键顶的垂直运动执行切换操作，安装在键顶下方的支撑板，布置在支撑板上的膜和布置在膜上的安装构件，中心 用于接收弹性开关的开口，以及允许将推动构件安装在其中的装配孔。

公开(公告)号：US09249728B2

公开(公告)日：2016-02-02

申请号：US13468218

申请日：2012-05-10

Applicant: Chan-Sun Lim ,  Myeong-Hyo Kim ,  Jong-Sub Shin ,  Young-Chang Shon ,  Jeong-Hun Lee

Inventor： Chan-Sun Lim ,  Myeong-Hyo Kim ,  Jong-Sub Shin ,  Young-Chang Shon ,  Jeong-Hun Lee

IPC: F02C7/08 ,  F02C6/16

CPC classification number: F02C7/08 ,  F02C6/16 ,  Y02E60/15

Abstract: A power generation system includes a compression unit which compresses a gas, a storage which stores the compressed gas output from the compression unit, a first expansion unit which generates first power and outputs a first exhaust gas, a heating unit which heats at least the stored gas output from the storage, a second expansion unit which generates second power and outputs a second exhaust gas, a first regenerator which performs a first heat exchange between the second exhaust gas and the stored gas output from the storage, to generate a first heat exchange gas used to generate the first power and a first regenerator gas, and a second regenerator which performs a second heat exchange between the first exhaust gas and the first regenerator gas to generate a second heat exchange gas used to generate the second power after heated at the heating unit.

Abstract translation: 发电系统包括压缩气体的压缩单元，存储从压缩单元输出的压缩气体的存储器，产生第一功率并输出第一排气的第一膨胀单元，至少加热存储的加热单元 从存储器输出的气体，产生第二功率并输出第二废气的第二膨胀单元，在第二排气和从储存器输出的储存气体之间进行第一热交换的第一再生器，以产生第一热交换 用于产生第一功率的气体和第一再生器气体;以及第二再生器，其在第一废气和第一再生器气体之间进行第二热交换，以产生用于在第二再生器加热后产生第二功率的第二热交换气体 加热单元

公开(公告)号：US08503260B2

公开(公告)日：2013-08-06

申请号：US13104262

申请日：2011-05-10

Applicant: Jeong-Tae Hwang ,  Jeong-Hun Lee

Inventor： Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC: G11C29/00 ,  G11C8/00

CPC classification number: G11C29/28

Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

Abstract translation: 一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试 基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

公开(公告)号：US20050288927A1

公开(公告)日：2005-12-29

申请号：US11153660

申请日：2005-06-15

Applicant: Do-Sung Kim ,  Dong-Soon Min ,  Kwan-Sik Yoo ,  Seung-Woo Chung ,  Jeong-Hun Lee

Inventor： Do-Sung Kim ,  Dong-Soon Min ,  Kwan-Sik Yoo ,  Seung-Woo Chung ,  Jeong-Hun Lee

IPC: H04M3/50 ,  G10L15/26

CPC classification number: G10L15/22 ,  H04M3/5166 ,  H04M2203/2011

Abstract: A QoS call routing system using a counselor and a speech recognition engine comprises a speech recognition engine for recognizing speech and outputting characters and speech recognition results; a first counselor group terminal for reproducing the client's speech file to a counselor of a first counselor group so that the counselor may recognize the speech when the speech recognition result by the speech recognition engine is less than a reference value; a second counselor group terminal for allowing a counselor of a second counselor group to hear the client's speech so that the counselor may recognize the speech when the recognition by the counselor of the first counselor group has failed; and an IVR server for controlling the engine and terminals to provide information to the client.

Abstract translation: 使用顾问和语音识别引擎的QoS呼叫路由系统包括用于识别语音并输出字符和语音识别结果的语音识别引擎; 第一顾问组终端，用于将顾客的语音文件再现给第一顾问组的顾问，使得当语音识别引擎的语音识别结果小于参考值时，辅导员可以识别语音; 第二辅导组织终端，允许第二顾问组的顾问听取客户的演讲，以便辅导员在第一顾问组的顾问的认可失败时可以承认该演讲; 以及用于控制引擎和终端以向客户端提供信息的IVR服​​务器。

公开(公告)号：US08659962B2

公开(公告)日：2014-02-25

申请号：US13404446

申请日：2012-02-24

Applicant: Jeong-Hun Lee

Inventor： Jeong-Hun Lee

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C29/021 ,  G11C11/40 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/40 ,  G11C29/48

Abstract: A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of test data periodically in response to a data reference voltage whose voltage level is determined in response to a level test code during a test operation period defined by a test entry command and a test exit command, and generate a test result signal by comparing a logic level of the comparison data with the logic level of the test data; and a test operation sensing signal generation unit configured to generate a test operation sensing signal that is activated in response to the test entry command and inactivated in response to the test result signal.

Abstract translation: 半导体器件包括：数据存储单元，被配置为接收输入数据，输出具有逻辑电平之间的电压电平差的输入数据，以及逻辑电平与输入数据区分的输出比较数据; 测试操作单元，被配置为响应于在由测试输入命令和测试退出命令所定义的测试操作期间响应于电平测试代码确定其电压电平的数据参考电压周期性地确定测试数据的逻辑电平， 并通过将比较数据的逻辑电平与测试数据的逻辑电平进行比较来产生测试结果信号; 以及测试操作感测信号生成单元，被配置为生成响应于测试输入命令被激活并且响应于测试结果信号而被去激活的测试操作感测信号。

公开(公告)号：US08386858B2

公开(公告)日：2013-02-26

申请号：US12616529

申请日：2009-11-11

Applicant: Jeong-Hun Lee ,  Jeong-Tae Hwang

Inventor： Jeong-Hun Lee ,  Jeong-Tae Hwang

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/46

Abstract: A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.

Abstract translation: 半导体存储器件能够在其各种操作模式下执行测试操作。 特别地，半导体存储器件可以进入其他模式的测试模式以及全部银行预充电模式。 半导体存储器件包括：测试模式控制块，被配置为在激活模式下产生预定间隔使能的测试信号;以及模式寄存器组控制模块，被配置为使得模式寄存器设置信号能够在预定间隔内进行测试操作 响应测试信号。

公开(公告)号：US20120155203A1

公开(公告)日：2012-06-21

申请号：US13104262

申请日：2011-05-10

Applicant: Jeong-Tae Hwang ,  Jeong-Hun Lee

Inventor： Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC: G11C29/18

CPC classification number: G11C29/28

Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

Abstract translation: 一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试 基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

公开(公告)号：US07983106B2

公开(公告)日：2011-07-19

申请号：US12494815

申请日：2009-06-30

Applicant: Yong-Mi Kim ,  Jeong-Tea Hwang ,  Jeong-Hun Lee

Inventor： Yong-Mi Kim ,  Jeong-Tea Hwang ,  Jeong-Hun Lee

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract translation: 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。

公开(公告)号：US08320212B2

公开(公告)日：2012-11-27

申请号：US13155901

申请日：2011-06-08

Applicant: Yong-Mi Kim ,  Jeong-Tae Hwang ,  Jeong-Hun Lee

Inventor： Yong-Mi Kim ,  Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract translation: 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。