公开(公告)号：US06911397B2

公开(公告)日：2005-06-28

申请号：US10412522

申请日：2003-04-11

申请人： Jin-Won Jun ,  Young-Wug Kim ,  Tae-Soo Park ,  Kyung-Tae Lee

发明人： Jin-Won Jun ,  Young-Wug Kim ,  Tae-Soo Park ,  Kyung-Tae Lee

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76807 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.

摘要翻译： 形成双镶嵌互连的方法采用低k介电有机聚合物作为绝缘层。 仅使用一个硬掩模层，使用与自对准间隔物的蚀刻速率不同的硬掩模层和蚀刻停止层来防止对绝缘层的灰化损伤。 此外，可以形成小于光刻工艺的分辨率极限的通孔。 结果，该过程被简化，并且不发生光致抗蚀剂尾部现象。

公开(公告)号：US20050158935A1

公开(公告)日：2005-07-21

申请号：US11037506

申请日：2005-01-18

申请人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

发明人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66553 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

摘要翻译： 在半导体器件中形成金属栅极的方法中，在衬底上形成栅极绝缘图案和伪栅极图案。 在伪栅极图案上形成绝缘中间层以覆盖伪栅极图案。 抛光绝缘夹层，使得裸露栅极图案的顶表面露出，并且选择性地去除伪栅极图案以在衬底上形成沟槽。 栅极间隔件形成在沟槽的内侧壁上，用于确定金属栅极的栅极长度。 将金属沉积到足够的厚度以填充沟槽以形成金属层。 金属层被抛光以保留在沟槽中。 因此，金属栅极的栅极长度可以减小到不超过光刻曝光系统的分辨率极限。

公开(公告)号：US07361565B2

公开(公告)日：2008-04-22

申请号：US11037506

申请日：2005-01-18

申请人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

发明人： Jeong-Ho Shin ,  Jong-Hyon Ahn ,  Kong-Soo Cheong ,  Jin-Won Jun

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

摘要翻译： 在半导体器件中形成金属栅极的方法中，在衬底上形成栅极绝缘图案和伪栅极图案。 在伪栅极图案上形成绝缘中间层以覆盖伪栅极图案。 抛光绝缘夹层，使得裸露栅极图案的顶表面露出，并且选择性地去除伪栅极图案以在衬底上形成沟槽。 栅极间隔件形成在沟槽的内侧壁上，用于确定金属栅极的栅极长度。 将金属沉积到足够的厚度以填充沟槽以形成金属层。 金属层被抛光以保留在沟槽中。 因此，金属栅极的栅极长度可以减小到不超过光刻曝光系统的分辨率极限。